# US 2021/0173618 A1 · Converting a boolean masked value to an arithmetically masked value for cryptographic operations

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- Number: US 2021/0173618 A1
- Document ID: US20210173618A1
- Status: Published application
- Kind: A1
- Application number: 17/124,374
- Filed: 2020-12-16
- Published: 2021-06-10
- Earliest claimed: 2016-03-03
- Assignees: Cryptography Research, Inc.
- Applicants: Cryptography Research, Inc.
- Inventors: Michael Hutter; Michael Tunstall
- Web page: https://patentgrep.com/patent/US20210173618A1

## CPC

- G06F 7/764: {Masking}
- G06F 7/00: Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00)
- G06F 7/58: Random or pseudo-random number generators
- G06F 7/588: {Random number generators, i.e. based on natural stochastic processes}
- G06F 21/72: in cryptographic circuits
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- H04L 9/002: {Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441)}
- H04L 9/06: the encryption apparatus using shift registers or memories for block-wise {or stream} coding, e.g. DES systems {or RC4; Hash functions; Pseudorandom sequence generators}
- H04L 9/14: using a plurality of keys or algorithms
- H04L 9/30: Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
- G06F 2207/7233: Masking, e.g. (A**e)+r mod n
- G06F 2221/2107: File encryption
- H04L 2209/04: Masking or blinding
- H04L 2209/046: of operations, operands or results of the operations
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A first input share value, a second input share value, and a third input share value may be received. The first input share value may be converted to a summation or subtraction between an input value and a combination of the second input share value and the third input share value. A random number value may be generated and combined with the second input share value and the third input share value to generate a combined value. Furthermore, a first output share value may be generated based on a combination of the converted first input share value, the combined value, and additional random number values.

## Claims

### Claim 1

(canceled)

### Claim 2

A system comprising:
a set of registers to store a first input share value, a second input share value, a third input share value, and a first output share value, wherein the first input share value represents a Boolean combination between an input value, the second input share value, and the third input share value;
a first circuit to perform a cryptographic operation based on a Boolean operation and an arithmetic operation; and
a second circuit coupled to the set of registers and the first circuit, wherein the second circuit is to:
convert the first input share value to a summation or subtraction between the input value and a combination of the second input share value and the third input share value;
generate a first random value;
combine the first random value with the second input share value and the third input share value to generate a combined value;
convert the combined value to a summation or subtraction between the first random value and a combination of the second input share value and the third input share value;
generate a second random value; and
generate the first output share value based on a combination of the converted first input share value, the converted combined value, and the second random value.

### Claim 3 (depends on 2)

The system of claim 2, wherein the second circuit is further to:
receive an indication that the cryptographic operation being performed by the first circuit has switched from using the Boolean operation to using the arithmetic operation; and
in response to the indication, receive the first input share value, the second input share value, the third input share value from the set of registers.

### Claim 4 (depends on 2)

The system of claim 2, wherein the set of registers is further to store a second output share value and a third output share value, wherein the first output share value represents an arithmetic combination between the input value, the second output share value, and the third output share value, wherein the second random value corresponds to the second output share value, wherein the second circuit is further to generate a third random value, wherein the third random value corresponds to the third output share value.

### Claim 5 (depends on 4)

The system of claim 4, wherein the second output share value and the third output share value are the same as the second input share value and the third input share value.

### Claim 6 (depends on 4)

The system of claim 4, wherein the second output share value and the third output share value are each different than the second input share value and the third input share value.

### Claim 7 (depends on 2)

The system of claim 2, wherein the second circuit is further to:
receive at least one additional input share value, wherein the second circuit is to generate the first output share value further based on the at least one additional input share value.

### Claim 8 (depends on 2)

The system of claim 2, wherein to combine the first random value with the second input share value and the third input share value to generate the combined value, the second circuit is further to:
at a first time, perform an XOR operation between the first random value and the second input share value to generate an intermediate value;
at a second time after the first time, perform the XOR operation between the intermediate value and the third input share value to generate a second intermediate value; and
convert the second intermediate value to the combined value.

### Claim 9 (depends on 2)

The system of claim 2, wherein to generate the first output share value, the second circuit is further to:
perform a summation or subtraction between the converted first input share value and at least the second random value; and
perform a subtraction operation between a result of the summation or subtraction and the combined value.

### Claim 10

A method comprising:
performing a cryptographic operation with a Boolean operation;
receiving a first input share value, a second input share value, and a third input share value;
converting the first input share value to a summation or subtraction between an input value and a combination of the second input share value and the third input share value;
generating a first random value;
combining the first random value with the second input share value and the third input share value to generate a combined value;
converting the combined value to a summation or subtraction between the first random value and a combination of the second input share value and the third input share value;
generating a second random value;
generating a first output share value based on a combination of the converted first input share value, the converted combined value, and the second random value; and
performing the cryptographic operation with an arithmetic operation by using the first output share value.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
receiving an indication that the cryptographic operation has switched from using the Boolean operation to using the arithmetic operation.

### Claim 12 (depends on 10)

The method of claim 10, wherein combining the first random value with the second input share value and the third input share value to generate the combined value comprises:
at a first time, performing an XOR operation between the first random value and the second input share value to generate an intermediate value;
at a second time after the first time, performing the XOR operation between the intermediate value and the third input share value to generate a second intermediate value; and
converting the second intermediate value to the combined value.

### Claim 13 (depends on 10)

The method of claim 10, wherein a second output share value and a third output share value associated with the first output share value are the same as the second input share value and the third input share value.

### Claim 14 (depends on 10)

The method of claim 10, wherein a second output share value and a third output share value associated with the first output share value are each different than the second input share value and the third input share value.

### Claim 15 (depends on 10)

The method of claim 10, further comprising:
receiving at least one additional input share value, wherein generating of the first output share value is further based on the at least one additional input share value.

### Claim 16 (depends on 10)

The method of claim 10, wherein combining the first random value with the second input share value and the third input share value to generate the combined value comprises:
at a first time, performing an XOR operation between the first random value and the second input share value to generate an intermediate value;
at a second time after the first time, performing the XOR operation between the intermediate value, the third input share value, and an additional random value to generate a second intermediate value; and
converting the second intermediate value to the combined value.

### Claim 17 (depends on 10)

The method of claim 10, wherein generating the first output share value comprises:
performing a summation or subtraction between the converted first input share value and the second random value and a third random value; and
performing a subtraction operation between a result of the summation or subtraction and the combined value.

### Claim 18

A non-transitory computer readable medium including data that, when accessed by a processing device, cause the processing device to perform operations comprising:
performing a cryptographic operation with a Boolean operation;
receiving a first input share value, a second input share value, and a third input share value;
converting the first input share value to a summation or subtraction between an input value and a combination of the second input share value and the third input share value;
generating a first random value;
combining the first random value with the second input share value and the third input share value to generate a combined value;
converting the combined value to a summation or subtraction between the first random value and a combination of the second input share value and the third input share value;
generating a second random value;
generating a first output share value based on a combination of the converted first input share value, the converted combined value, and the second random value; and
performing the cryptographic operation with an arithmetic operation by using the first output share value.

### Claim 19 (depends on 18)

The non-transitory computer readable medium of claim 18, the operations further comprising:
receiving an indication that the cryptographic operation has switched from using the Boolean operation to using the arithmetic operation.

### Claim 20 (depends on 18)

The non-transitory computer readable medium of claim 18, wherein to combine the first random value with the second input share value and the third input share value to generate the combined value, the operations further comprise:
at a first time, performing an XOR operation between the first random value and the second input share value to generate an intermediate value;
at a second time after the first time, performing the XOR operation between the intermediate value and the third input share value to generate a second intermediate value; and
converting the second intermediate value to the combined value.

### Claim 21 (depends on 18)

The non-transitory computer readable medium of claim 18, wherein a second output share value and a third output share value associated with the first output share value are the same as the second input share value and the third input share value.