Asynchronous processor architecture

A computing device for processing data, said processing operation being able to be broken down into a set of elementary operations to be performed, said device comprising:

• a control unit;
• at least one first arithmetic logic unit from among a plurality;
• a set of registers able to supply data forming an operand to the inputs of said arithmetic logic units and able to be supplied with data from the outputs of said arithmetic logic units;
• a memory;
• a memory interface by way of which data are transmitted and routed between the registers and the memory;
• said computing device being configured so as to:
• a) obtain the memory addresses of each of the data absent from the registers and forming an operand for at least one of said elementary operations to be performed and;
• b) read each of said data from memory by way of the obtained memory addresses in order to load them into the registers via the memory interface;
• c) transmit an instruction to execute computing operations from the control unit to said first arithmetic logic unit, said instruction not containing any addressing instruction;
• d) upon receiving said instruction to execute computing operations, and as soon as the operands are available on the registers, execute all of said elementary operations by way of said first arithmetic logic unit receiving, at input, each of the operands from the registers;
• e) store the data forming results of the processing operation on the registers at output of said first arithmetic logic unit;
• f) obtain a memory address for each of the data forming a result of the processing operation;
• g) write each of the data forming a result of the processing operation from the registers to memory for storage and via the memory interface, by way of the obtained memory addresses.