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US 2021/0135007 A1Published application
Method for fabricating transistor with thinned channel
AssigneeIntel Corporation
InventorsJustin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
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Abstract
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
Claims20
An apparatus comprising:
- a processor;
- and
- a network interface coupled to the processor via a bus, wherein the processor includes a non-planar transistor comprising:
- a gate electrode comprising a tri-gate structure;
- a semiconductor body;
- and
- a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric is a dual layer gate dielectric having a first structure and a second structure, wherein the second structure is different and separate from the first structure, wherein the first structure comprises Si and O, and wherein the second structure comprises Hf and O.
4 more elements
A method for forming a non-planar transistor, the method comprising:
- forming a gate electrode comprising a tri-gate structure;
- forming a three-dimensional semiconductor body;
- and
- forming a gate dielectric between the gate electrode and the three-dimensional semiconductor body, wherein the gate dielectric is a dual layer gate dielectric having a first structure and a second structure, wherein the second structure is different and separate from the first structure, wherein the first structure comprises Si and O, and wherein the second structure comprises Hf and O.
1 more element
A non-planar transistor comprising:
- a gate electrode comprising a tri-gate structure;
- a three-dimensional semiconductor body;
- and
- a gate dielectric between the gate electrode and the three-dimensional semiconductor body, wherein the gate dielectric is a dual layer gate dielectric having a first structure and a second structure, wherein the second structure is different and separate from the first structure, wherein the first structure comprises Si and O, and wherein the second structure comprises Hf and O, wherein the gate electrode has a work function of 5.2 eV or less than 5.2 eV.
1 more element
Dependencies are inferred from the claim text.