Sub-sampling phase-locked loop
AssigneeRealtek Semiconductor Corp.
InventorsYu-Che Yang, Ka-Un Chan, Yong-Ru Lu, Shen-Iuan Liu
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Abstract
The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.
Claims11
A sub-sampling phase-locked loop (PLL), comprising:
- a first phase detector, configured to use a reference clock signal to sample a feedback signal to generate a first phase detection result;
- a first charge pump, coupled to the first phase detector, configured to generate a first signal according to the first phase detection result and a pulse signal;
- an oscillator, coupled to the first charge pump, configured to generate an output clock signal according to the first signal;
- and
- a first buffer, coupled to the oscillator, configured to receive the output clock signal to generate the feedback signal, and control a slew rate of the feedback signal according to a slew rate control signal.
A sub-sampling phase-locked loop (PLL), comprising:
- a phase detector, configured to use a reference clock signal to sample a feedback signal to generate a phase detection result;
- a pulse signal generating circuit, configured to generate a pulse signal according to the reference clock signal;
- a charge pump, coupled to the phase detector, configured to generate a control signal according to the phase detection result and the pulse signal;
- an oscillator, coupled to the charge pump, configured to generate an output clock signal according to the control signal;
- and
- a pulse width control circuit, configured to refer to the output clock signal to generate a pulse width control signal to the pulse signal generating circuit, to control a pulse width of the pulse signal.
Dependencies are inferred from the claim text.