Method and System for Providing a Configurable Logic Device Having a Programmable DSP Block

A method of programmable digital signal processing (“DSP”) block in a field programmable gate array (“FPGA”) configured to processing data, comprising:

• receiving a first A operand having a first A bit number and a first B operand having a first B bit number;
• receiving a second A operation having a second A bit number and a second B operand having a second B bit number;
• multiplying, by a first multiplier in a programmable DSP block, the first A operand by the first B operand to produce a first product result;
• multiplying, by a second multiplier in the programmable DSP block, the second A operand by the second B operand to produce a second product result;
• and
• combining the first product result and the second product result to generate an output result for the programmable DSP block.

A programmable logic device having a programmable digital signal processing (“DSP”) block operable to be selectively programmed to perform one or more logic functions, the device comprising:

• a plurality of configurable logic blocks (“LBs”) able to be selectively programmed to perform one or more logic functions;
• an input and output (“I/O”) block coupled to the plurality of configurable LBs and configured to have a plurality of I/O ports for facilitating data transfer;
• and
• a plurality of configurable DSPs (“CDSPs”) coupled to the plurality of configurable LBs and configured to perform one or more selected predefined logic functions, wherein each of the plurality of CDSPs includes a 27×18 multiplier and a 12×12 multiplier.