# US 2021/0083085 A1 · Semiconductor device and fabricating method thereof

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- Number: US 2021/0083085 A1
- Document ID: US20210083085A1
- Status: Published application
- Kind: A1
- Application number: 16/659,579
- Filed: 2019-10-22
- Published: 2021-03-18
- Earliest claimed: 2019-09-12
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chun-Ming Chang; Wen-Jung Liao
- Web page: https://patentgrep.com/patent/US20210083085A1

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 48/30: Devices controlled by electric currents or voltages
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 84/01: Manufacture or treatment
- H10D 84/05: using Group III-V technology
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/82: of only field-effect components
- H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices
- H10W 10/01: {Manufacture or treatment}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a group III-V gate structure and a group III-V patterned structure. The group III-V body layer and the group III-V barrier layer are disposed on the substrate. The group III-V gate structure is disposed on the group III-V barrier layer within the active region. The group III-V patterned structure is disposed on the group III-V barrier layer within the isolation region. The composition of the group III-V patterned structure is the same as the composition of the group III-V gate structure.

## Claims

### Claim 1

A semiconductor device, comprising:
an enhancement mode high electron mobility transistor comprising an active region and an isolation region, wherein the enhancement mode high electron mobility transistor comprises:
a substrate;
a group III-V body layer and a group III-V barrier layer disposed on the substrate;
a group III-V gate structure disposed on the group III-V barrier layer in the active region; and
a group III-V patterned structure disposed on the group III-V barrier layer in the isolation region, wherein a composition of the group III-V patterned structure is the same as a composition of the group III-V gate structure.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a bottom surface of the group III-V gate structure is aligned with a bottom surface of the group III-V patterned structure.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the composition of the group III-V gate structure and the composition of the group III-V patterned structure are p-type GaN or p-type AlGaN.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising an etch stop layer disposed between the group III-V patterned structure and the group III-V barrier layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising an etch mask layer disposed on the top surfaces of the group III-V gate structure and the group III-V patterned structure.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein a composition of the etch mask layer comprises silicon nitride or silicon oxide.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a passivation layer disposed on the group III-V gate structure and the group III-V patterned structure.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising an etch mask layer disposed between the passivation layer and the group III-V patterned structure.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein a composition of the passivation layer comprises aluminum nitride, aluminum oxide or silicon nitride.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, further comprising another enhancement mode high electron mobility transistor disposed on one side of the enhancement mode high electron mobility transistor, wherein a portion of the group III-V patterned structure is continuously disposed between the enhancement mode high electron mobility transistors.

### Claim 11

A method of fabricating a semiconductor device comprising an active region and an isolation region, wherein the method comprises:
providing a substrate having a group III-V body layer, a group III-V barrier layer, and a group III-V gate layer thereon; and
patterning the group III-V gate layer to form a group III-V gate structure in the active region and a group III-V patterned structure in the isolation region.

### Claim 12 (depends on 11)

The method of fabricating the semiconductor device according to claim 11, wherein the group III-V gate structure and the group III-V patterned structure are formed concurrently.

### Claim 13 (depends on 11)

The method of fabricating the semiconductor device according to claim 11, further comprising:
forming a patterned etch mask layer on the group III-V gate layer; and
etching the group III-V gate layer by using the patterned etch mask layer as an etch mask.

### Claim 14 (depends on 13)

The method of fabricating the semiconductor device according to claim 13, further comprising depositing a passivation layer on the group III-V gate structure and the group III-V patterned structure.

### Claim 15 (depends on 14)

The method of fabricating the semiconductor device according to claim 14, wherein a composition of the passivation layer comprises aluminum nitride, aluminum oxide or silicon nitride.

### Claim 16 (depends on 14)

The method of fabricating the semiconductor device according to claim 14, wherein the etch mask layer is disposed between the passivation layer and the group III-V patterned structure.

### Claim 17 (depends on 14)

The method of fabricating the semiconductor device according to claim 14, further comprising forming a gate electrode and at least two source/drain electrodes penetrating the passivation layer respectively, wherein the electrodes are spaced apart from the group III-V patterned structure.

### Claim 18 (depends on 11)

The method of fabricating the semiconductor device according to claim 11, wherein a bottom surface of the group III-V gate structure is aligned with a bottom surface of the group III-V patterned structure.

### Claim 19 (depends on 11)

The method of fabricating the semiconductor device according to claim 11, wherein s composition of the group III-V gate structure and a composition of the group III-V patterned structure are p-type GaN or p-type AlGaN.

### Claim 20 (depends on 11)

The method of fabricating the semiconductor device according to claim 11, wherein an etch stop layer is disposed on the substrate, and the etch stop layer is disposed between the group III-V barrier layer and the group III-V gate layer.