# US 2021/0083084 A1 · Semiconductor device and fabricating method thereof

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- Number: US 2021/0083084 A1
- Document ID: US20210083084A1
- Status: Published application
- Kind: A1
- Application number: 16/655,252
- Filed: 2019-10-17
- Published: 2021-03-18
- Earliest claimed: 2019-09-12
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chun-Ming Chang; Wen-Jung Liao
- Web page: https://patentgrep.com/patent/US20210083084A1

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/149: {Source or drain regions of field-effect devices}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer in the active region.

## Claims

### Claim at position 1

1: A semiconductor device, comprising:
an enhancement mode high electron mobility transistor (HEMT) comprising an active region and an isolation region, wherein the enhancement mode HEMT comprises:
a substrate;
a group III-V body layer, disposed on the substrate;
a group III-V barrier layer, disposed on the group III-V body layer in the active region and the isolation region, wherein the group III-V barrier layer comprises a first thickness and a second thickness which are different from each other in the active region; and
a recess, disposed in the group III-V barrier layer in the active region.

### Claim at position 2 (depends on 1)

2: The semiconductor device of claim 1, wherein the group III-V barrier layer in the active region has the first thickness between 2 and 10 nm.

### Claim at position 3 (depends on 1)

3: The semiconductor device of claim 1, further comprising a gate electrode disposed in the recess and electrically coupled to the group III-V barrier layer in the active region.

### Claim at position 4 (depends on 1)

4: The semiconductor device of claim 1, wherein the semiconductor device further comprises at least two source/drain electrodes disposed in the active region.

### Claim at position 5 (depends on 1)

5: The semiconductor device of claim 1, further comprising an etch mask layer disposed on a top surface of the group III-V barrier layer and spaced apart from the recess.

### Claim at position 6 (depends on 5)

6: The semiconductor device of claim 5, wherein a composition of the etch mask layer comprises silicon nitride or silicon oxide.

### Claim at position 7 (depends on 1)

7: The semiconductor device of claim 1, wherein the semiconductor device further comprises another recess disposed in the group III-V barrier layer of the isolation region.

### Claim at position 8 (depends on 7)

8: The semiconductor device of claim 7, wherein the group III-V barrier layer in the isolation region has a thickness between 2 and 10 nm.

### Claim at position 9 (depends on 7)

9: The semiconductor device of claim 7, wherein the semiconductor device further comprises a passivation layer disposed in the recesses of the active region and the isolation region.

### Claim at position 10 (depends on 9)

10: The semiconductor device of claim 9, further comprising an etch mask layer disposed between the passivation layer and the group III-V barrier layer in the active region, wherein the etch mask layer is spaced apart from bottoms of the recesses in the active region and the isolation region.

### Claim at position 11 (depends on 9)

11: The semiconductor device of claim 9, wherein a composition of the passivation layer comprises aluminum nitride, aluminum oxide or silicon nitride.

### Claim at position 12 (depends on 1)

12: The semiconductor device of claim 1, further comprising another enhancement mode high electron mobility transistor disposed on a side of the enhancement mode HEMT, wherein the group III-V barrier layer is a continuous layer disposed between the enhancement mode HEMTs.

### Claim at position 13

13: A method of fabricating a semiconductor device comprising an active region and an isolation region, the method comprising:
providing a substrate having a group III-V body layer and a group III-V barrier layer thereon;
forming a first recess and a second recess in the group III-V barrier layer, wherein the first recess and the second recess are in the active region and the isolation region respectively; and
depositing a passivation layer at bottoms of the first recess and the second recess, wherein portions of the group III-V barrier layer is disposed under the first recess and the second recess.

### Claim at position 14 (depends on 13)

14: The method of fabricating the semiconductor device of claim 13, wherein the first recess and the second recess are formed concurrently.

### Claim at position 15 (depends on 13)

15: The method of fabricating the semiconductor device of claim 13, wherein the group III-V barrier layer in the active region has a thickness between 2 and 10 nm.

### Claim at position 16 (depends on 13)

16: The method of fabricating the semiconductor device of claim 13, wherein a composition of the passivation layer comprises aluminum nitride, aluminum oxide or silicon nitride.

### Claim at position 17 (depends on 13)

17: The method of fabricating the semiconductor device of claim 13, further comprising:
forming a patterned etch mask layer on the group III-V barrier layer; and
etching the group III-V barrier layer by using the patterned etch mask as an etch mask.

### Claim at position 18 (depends on 17)

18: The method of fabricating the semiconductor device of claim 17, wherein a composition of the etch mask layer comprises silicon nitride or silicon oxide.

### Claim at position 19 (depends on 17)

19: The method of fabricating a semiconductor device of claim 17, wherein the etch mask layer is disposed between the passivation layer and the group III-V barrier layer in the active region.

### Claim at position 20 (depends on 17)

20: The method of fabricating a semiconductor device of claim 17, further comprising forming a gate electrode and at least two source/drain electrodes respectively penetrating the passivation layer, wherein the electrodes are spaced apart from the group III-V barrier layer at the bottom of the second recess.