Vertical cross-point arrays for ultra-high-density memory applications

A vertical cross-point array (VCPA) comprising:

• a plurality of horizontal line layers, each horizontal line layer comprising a plurality of horizontal lines;
• a plurality of rows of vertical lines interleaved with the horizontal lines of said plurality of horizontal line layers, such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer;
• and
• a plurality of conductive metal oxide (CMO)-based memory cells formed at intersections of the horizontal lines and the vertical lines,
• wherein each vertical line comprises a center conductor surround by an inner CMO layer and an outer insulating metal oxide (IMO) layer,
• wherein each horizontal line comprises a conductive line bounded on both sides by an inner diffusion barrier layer and an outer edge electrode layer, and
• wherein each CMO-based memory cell is disposed between the center conductor of a vertical line and the outer edge electrode layer of an adjacent horizontal line.

A memory structure comprising:

• a vertical cross-point array (VCPA) comprising:
• a plurality of horizontal line layers, each horizontal line layer comprising a plurality of horizontal lines;
• a plurality of rows of vertical lines interleaved with the horizontal lines of said plurality of horizontal line layers, such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer;
• and
• a plurality of conductive metal oxide (CMO)-based memory cells formed at intersections of the horizontal lines and the vertical lines,
• wherein each vertical line comprises a center conductor surround by an inner CMO layer and an outer insulating metal oxide (IMO) layer,
• wherein each horizontal line comprises a conductive line bounded on both sides by an inner diffusion barrier layer and an outer edge electrode layer, and
• wherein each CMO-based memory cell is disposed between the center conductor of a vertical line and the outer edge electrode layer of an adjacent horizontal line;
• an upper bit line layer above said VCPA having a first plurality of horizontal bit lines;
• and
• a lower bit line layer below said VCPA having a second plurality of horizontal bit lines.

A vertical cross-point array (VCPA) comprising:

• a plurality of back-end of the line (BEOL) horizontal line layers, each horizontal line layer comprising a plurality of horizontal lines;
• a plurality of rows of BEOL vertical lines interleaved with the horizontal lines of said plurality of horizontal line layers, such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer;
• and
• a plurality of BEOL conductive metal oxide (CMO)-based memory cells formed at intersections of the horizontal lines and the vertical lines,
• wherein each vertical line comprises a center conductor surround by an inner CMO layer and an outer insulating metal oxide (IMO) layer,
• wherein each horizontal line comprises a conductive line bounded on both sides by an inner diffusion barrier layer and an outer edge electrode layer, and
• wherein each CMO-based memory cell is disposed between the center conductor of a vertical line and the outer edge electrode layer of an adjacent horizontal line.