# US 2021/0083000 A1 · Nonvolatile memory device

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- Number: US 2021/0083000 A1
- Document ID: US20210083000A1
- Status: Published application
- Kind: A1
- Application number: 16/817,078
- Filed: 2020-03-12
- Published: 2021-03-18
- Earliest claimed: 2019-09-18
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Yoshinori KUMURA
- Web page: https://patentgrep.com/patent/US20210083000A1

## CPC

- H10B 61/10: {comprising components having two electrodes, e.g. diodes or MIM elements}
- H10N 50/01: Manufacture or treatment
- H10N 50/80: Constructional details
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

According to one embodiment, a nonvolatile memory device includes a plurality of wiring line pairs each including a pair of first and second wiring lines extending in a first direction, a plurality of third wiring lines each extending in a second direction intersecting the first direction, and a plurality of memory cells provided between the wiring line pairs and the third wiring lines. Each of the memory cells includes a resistance change memory element connected to the third wiring line, and a switching element structure including a first switching element portion provided between the resistance change memory element and the first wiring line, and a second switching element portion provided between the resistance change memory element and the second wiring line.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a plurality of wiring line pairs each including a pair of first and second wiring lines extending in a first direction;
a plurality of third wiring lines each extending in a second direction intersecting the first direction; and
a plurality of memory cells provided between the wiring line pairs and the third wiring lines,
each of the memory cells comprising:
a resistance change memory element connected to a corresponding third wiring line, and
a switching element structure including a first switching element portion provided between the resistance change memory element and the first wiring line included in a corresponding wiring line pair, and a second switching element portion provided between the resistance change memory element and the second wiring line included in the corresponding wiring line pair.

### Claim 2 (depends on 1)

The device of claim 1, wherein
the first switching element portion includes a first portion of a switching element material layer provided between the resistance change memory element and the first wiring line included in the corresponding wiring line pair, and
the second switching element portion includes a second portion of the switching element material layer provided between the resistance change memory element and the second wiring line included in the corresponding wiring line pair.

### Claim 3 (depends on 2)

The device of claim 2, wherein
the first portion of the switching element material layer and the second portion of the switching element material layer are provided continuously via a third portion of the switching element material layer.

### Claim 4 (depends on 3)

The device of claim 3, wherein a thickness of the third portion of the switching element material layer is thinner than a thickness of the first portion of the switching element material layer and a thickness of the second portion of the switching element material layer.

### Claim 5 (depends on 2)

The device of claim 2, wherein the first portion of the switching element material layer and the second portion of the switching element material layer are separated from each other.

### Claim 6 (depends on 2)

The device of claim 2, wherein the switching element material layer is provided continuously between adjacent memory cells.

### Claim 7 (depends on 2)

The device of claim 2, wherein the switching element material layer is separated between adjacent memory cells.

### Claim 8 (depends on 1)

The device of claim 1, further comprising a plurality of selection circuits each selecting one of the first wiring line and the second wiring line included in the corresponding wiring line pair.

### Claim 9 (depends on 8)

The device of claim 8, wherein each of the selection circuit selects, if the first switching element portion included in one of the memory cells connected to the corresponding wiring line pair is defective, the second wiring line included in the corresponding wiring line pair.

### Claim 10 (depends on 8)

The device of claim 8, wherein each of the selection circuits switches the first wiring line to the second wiring line included in the corresponding wiring line pair based on a predetermined number of rewrites.

### Claim 11 (depends on 1)

The device of claim 1, wherein each of the first switching element portion and the second switching element portion has a nonlinear current-voltage characteristic.

### Claim 12 (depends on 1)

The device of claim 1, wherein each of the first switching element portion and the second switching element portion exhibits an off state when a voltage applied thereto is smaller than a predetermined voltage, and exhibits an on state if a voltage applied thereto is greater than the predetermined voltage.

### Claim 13 (depends on 1)

The device of claim 1, wherein read or write is performed on the resistance change memory element by setting one of the first switching element portion and the second switching element portion included in the corresponding wiring line pair to an on state.

### Claim 14 (depends on 1)

The device of claim 1, wherein the resistance change memory element is a magnetoresistive element.