# US 2021/0082971 A1 · Array substrate, liquid crystal panel and liquid crystal display device

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- Number: US 2021/0082971 A1
- Document ID: US20210082971A1
- Status: Published application
- Kind: A1
- Application number: 16/076,220
- Filed: 2018-05-10
- Published: 2021-03-18
- Earliest claimed: 2017-12-22
- Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd
- Inventors: Yuanfu LIU
- Web page: https://patentgrep.com/patent/US20210082971A1

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)}
- G02F 1/136213: {Storage capacitors associated with the pixel electrode}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G02F 2201/124: interdigital
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

An array substrate is disclosed. The array substrate includes a semiconductor active layer, a gate insulation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, a planarization layer and a passivation layer sequentially disposed on a base substrate; wherein the array substrate is provided with a row driving unit, including a capacitor structure; wherein the capacitor structure includes a first capacitive plate formed in the semiconductor active layer, a second capacitive plate formed in the first metal layer and a third capacitive plate formed in the second metal layer; and wherein projections of the first capacitive plate and the second capacitive plate on the base substrate are partially overlapped, projections the second capacitive plate and the third capacitive plate on the base substrate are partially overlapped and the third capacitive plate is electrically connected to the first capacitive plate through a first via hole.

## Claims

### Claim 1

An array substrate, comprising:
a semiconductor active layer, a gate insulation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, a planarization layer and a passivation layer which are sequentially disposed on a base substrate;
wherein the array substrate is provided with a row driving unit, and the row driving unit includes a capacitor structure;
wherein the capacitor structure includes a first capacitive plate, a second capacitive plate and a third capacitive plate, wherein the first capacitive plate is formed in the semiconductor active layer, the second capacitive plate is formed in the first metal layer and the third capacitive plate is formed in the second metal layer; and
wherein projections of the first capacitive plate and the second capacitive plate on the base substrate are partially overlapped, projections the second capacitive plate and the third capacitive plate on the base substrate are partially overlapped and the third capacitive plate is electrically connected to the first capacitive plate through a first via hole.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein a thickness of a portion of the interlayer dielectric layer in the capacitor structure is H1, and a thickness of a portion of the interlayer dielectric layer located outside the capacitor structure is H2, and H1<H2.

### Claim 3 (depends on 1)

The array substrate according to claim 1, wherein a material of the semiconductor active layer is poly-silicon, a material of each of the gate insulating layer and the interayer dielectric layer is SiOx, SiNx or a combination of SiOx and SiNx, a material of each of the first metal layer and the second metal layer is selected from one or a combination of two or more of Cr, W, Ti, Ta, Mo, Ai, and Cu.

### Claim 4 (depends on 1)

The array substrate according to claim 1, wherein the array substrate further comprises a planarization layer, a third metal layer and a passivation layer which are sequentially disposed on the second metal layer, the capacitor structure further includes a fourth capacitive plate, the fourth capacitive plate is formed in the third metal layer, projections of the fourth capacitive plate and the third capacitive plate on the base substrate are at least partially overlapped and the fourth capacitive plate is electrically connected to the second capacitive plate through the second via hole.

### Claim 5 (depends on 4)

The array substrate according to claim 4, wherein a material of each of the planarization layer and the passivation layer is SiOx, SiNx or a combination of SiOx and SiNx, a material of the third metal layer is selected from one or a combination of two or more of Cr, W, Ti, Ta, Mo, Al, and Cu.

### Claim 6 (depends on 4)

The array substrate according to claim 4, wherein the array substrate further comprises a pixel electrode layer disposed on the passivation layer, the capacitor structure further includes a fifth capacitive plate, the fifth capacitive plate is formed in the pixel electrode layer, projections of the fifth capacitive plate and the fourth capacitive plate are on the base substrate are at least partially overlapped and the fifth capacitive plate is electrically connected to the third capacitive plate through a third via hole.

### Claim 7 (depends on 6)

The array substrate according to claim 6, wherein a thickness of a portion of the passivation layer located in the capacitor structure is H3, a thickness of the passivation layer located outside the capacitor structure is H4, and H3<H4.

### Claim 8

A liquid crystal panel, comprising:
an array substrate and a color filter substrate which are disposed oppositely;
a liquid crystal layer disposed between the array substrate and the color filter substrate;
wherein the array substrate, comprises:
a semiconductor active layer, a gate insulation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, a planarization layer and a passivation layer which are sequentially disposed on a base substrate;
wherein the array substrate is provided with a row driving unit, and the row driving unit includes a capacitor structure;
wherein the capacitor structure includes a first capacitive plate, a second capacitive plate and a third capacitive plate, wherein the first capacitive plate is formed in the semiconductor active layer, the second capacitive plate is formed in the first metal layer and the third capacitive plate is formed in the second metal layer; and
wherein projections of the first capacitive plate and the second capacitive plate on the base substrate are partially overlapped, projections the second capacitive plate and the third capacitive plate on the base substrate are partially overlapped and the third capacitive plate is electrically connected to the first capacitive plate through a first via hole.

### Claim 9 (depends on 8)

The liquid crystal panel according to claim 8, wherein a thickness of a portion of the interlayer dielectric layer in the capacitor structure is H1, and a thickness of a portion of the interlayer dielectric layer located outside the capacitor structure is H2, and H1<H2.

### Claim 10 (depends on 8)

The liquid crystal panel according to claim 8, wherein a material of the semiconductor active layer is poly-silicon, a material of each of the gate insulating layer and the interlayer dielectric layer is SiOx, SiNx or a combination of SiOx and SiNx, a material of each of the first metal layer and the second metal layer is selected from one or a combination of two or more of Cr, W, Ti, Ta, Mo, Al, and Cu.

### Claim 11 (depends on 8)

The liquid crystal panel according to claim 8, wherein the array substrate further comprises a planarization layer, a third metal layer and a passivation layer which are sequentially disposed on the second metal layer, the capacitor structure further includes a fourth capacitive plate, the fourth capacitive plate is formed in the third metal layer, projections of the fourth capacitive plate and the third capacitive plate on the base substrate are at least partially overlapped and the fourth capacitive plate is electrically connected to the second capacitive plate through the second via hole.

### Claim 12 (depends on 11)

The liquid crystal panel according to claim 11, wherein a material of each of the planarization layer and the passivation layer is SiOx, SiNx or a combination of SiOx and SiNx, a material of the third metal layer is selected from one or a combination of two or more of Cr, W, Ti, Ta, Mo, Al, and Cu.

### Claim 13 (depends on 11)

The liquid crystal panel according to claim 11, wherein the array substrate further comprises a pixel electrode layer disposed on the passivation layer, the capacitor structure further includes a fifth capacitive plate, the fifth capacitive plate is formed in the pixel electrode layer, projections of the fifth capacitive plate and the fourth capacitive plate are on the base substrate are at least partially overlapped and the fifth capacitive plate is electrically connected to the third capacitive plate through a third via hole.

### Claim 14 (depends on 13)

The liquid crystal panel according to claim 13, wherein a thickness of a portion of the passivation layer located in the capacitor structure is H3, a thickness of the passivation layer located outside the capacitor structure is H4, and H3<H4.

### Claim 15

A liquid crystal display device, comprising:
a liquid crystal panel and a backlight module;
wherein the liquid crystal panel includes an array substrate and a color filter substrate which are disposed oppositely; and a liquid crystal layer disposed between the array substrate and the color filter substrate; and
wherein the array substrate, comprises:
a semiconductor active layer, a gate insulation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, a planarization layer and a passivation layer which are sequentially disposed on a base substrate;
wherein the array substrate is provided with a row driving unit, and the row driving unit includes a capacitor structure;
wherein the capacitor structure includes a first capacitive plate, a second capacitive plate and a third capacitive plate, wherein the first capacitive plate is formed in the semiconductor active layer, the second capacitive plate is formed in the first metal layer and the third capacitive plate is formed in the second metal layer; and
wherein projections of the first capacitive plate and the second capacitive plate on the base substrate are partially overlapped, projections the second capacitive plate and the third capacitive plate on the base substrate are partially overlapped and the third capacitive plate is electrically connected to the first capacitive plate through a first via hole.

### Claim 16 (depends on 15)

The liquid crystal display device according to claim 15, wherein a thickness of a portion of the interlayer dielectric layer in the capacitor structure is H1, and a thickness of a portion of the interlayer dielectric layer located outside the capacitor structure is H2, and H1<H2.

### Claim 17 (depends on 15)

The liquid crystal display device according to claim 15, wherein a material of the semiconductor active layer is poly-silicon, a material of each of the gate insulating layer and the interlayer dielectric layer is SiOx, SiNx or a combination of SiOx and SiNx, a material of each of the first metal layer and the second metal layer is selected from one or a combination of two or more of Cr, W, Ti, Ta, Mo, Al, and Cu.

### Claim 18 (depends on 15)

The liquid crystal display device according to claim 15, wherein the array substrate further comprises a planarization layer, a third metal layer and a passivation layer which are sequentially disposed on the second metal layer, the capacitor structure further includes a fourth capacitive plate, the fourth capacitive plate is formed in the third metal layer, projections of the fourth capacitive plate and the third capacitive plate on the base substrate are at least partially overlapped and the fourth capacitive plate is electrically connected to the second capacitive plate through the second via hole.

### Claim 19 (depends on 18)

The liquid crystal display device according to claim 18, wherein the array substrate further comprises a pixel electrode layer disposed on the passivation layer, the capacitor structure further includes a fifth capacitive plate, the fifth capacitive plate is formed in the pixel electrode layer, projections of the fifth capacitive plate and the fourth capacitive plate are on the base substrate are at least partially overlapped and the fifth capacitive plate is electrically connected to the third capacitive plate through a third via hole.

### Claim 20 (depends on 19)

The liquid crystal display device according to claim 19, wherein a thickness of a portion of the passivation layer located in the capacitor structure is H3, a thickness of the passivation layer located outside the capacitor structure is H4, and H3<H4.