# US 2021/0082965 A1 · Method for Manufacturing Thin Film Transistor, Thin Film Transistor, and Display Apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082965 A1 - Document ID: US20210082965A1 - Status: Published application - Kind: A1 - Application number: 16/756,934 - Filed: 2020-03-23 - Published: 2021-03-18 - Earliest claimed: 2019-05-22 - Assignees: Chengdu Cec Panda Display Technology Co., Ltd. - Applicants: Chengdu Cec Panda Display Technology Co., Ltd. - Inventors: Shuaiyi WANG; Hui TANG; Peng GAO; Ke ZENG; Xiangfeng LI - Web page: https://patentgrep.com/patent/US20210082965A1 ## CPC - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10P 34/40: with high-energy radiation - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure provides a method for manufacturing a thin film transistor, a thin film transistor, and a display apparatus. The method for manufacturing a thin film transistor includes: forming a gate layer on a substrate; forming a gate insulating layer on the gate layer; forming an active layer on the gate insulating layer; forming a source/drain layer on the active layer; and performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed, and controlling the plasma bombardment treatment to be performed at a gas flow rate of 4K sccm to 70K sccm, at a pressure of 600 mTorr to 1200 mTorr, at a power of 4 KW to 12 KW for a treatment time of 10 s to 60 s. ## Claims ### Claim 1 A method for manufacturing a thin film transistor, comprising: forming a gate layer on a substrate; forming a gate insulating layer on the gate layer; forming an active layer on the gate insulating layer; forming a source/drain layer on the active layer; and performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed, and controlling the plasma bombardment treatment to be performed at a gas flow rate of 4K sccm to 70K sccm, at a pressure of 600 mTorr to 1200 mTorr, at a power of 4 KW to 12 KW for a treatment time of 10 s to 60 s. ### Claim 2 (depends on 1) The method for manufacturing a thin film transistor according to claim 1, wherein the performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed comprises: performing the plasma bombardment treatment by using at least one gas of N2O, O2, Ar, and N2 on the surface of the active layer on which the source/drain layer is formed, and controlling the gas flow rate in a range of 4K sccm to 70K sccm, the pressure in a range of 600 mTorr to 1200 mTorr, the power in a range of 4 KW to 12 KW, and the treatment time in a range of 10 s to 60 s. ### Claim 3 (depends on 1) The method for manufacturing a thin film transistor according to claim 1, wherein the performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed comprises: performing the plasma bombardment treatment by using one gas of N2O, O2, Ar, and N2 on the surface of the active layer on which the source/drain layer is formed, and controlling the gas flow rate in a range of 30K sccm to 70K sccm, the pressure in a range of 600 mTorr to 1200 mTorr, the power in a range of 4 KW to 12 KW, and the treatment time in a range of 10 s to 40 s. ### Claim 4 (depends on 1) The method for manufacturing a thin film transistor according to claim 1, wherein the performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed comprises: performing the plasma bombardment treatment by using two gases of N2O, O2, Ar, and N2 on the surface of the active layer on which the source/drain layer is formed, and controlling the gas flow rate in a range of 4K sccm to 8K sccm, the pressure in a range of 600 mTorr to 1200 mTorr, the power in a range of 3 KW to 9 KW, and the treatment time in a range of 10 s to 60 s. ### Claim 5 (depends on 2) The method for manufacturing a thin film transistor according to claim 2, wherein a ratio of the gas flow rates of the two gases of N2O, O2, Ar, and N2 is between 1:4 and 4:1. ### Claim 6 (depends on 1) The method for manufacturing a thin film transistor according to claim 1, wherein the performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed comprises: performing the plasma bombardment treatment by using three gases of N2O, O2, Ar, and N2 on the surface of the active layer on which the source/drain layer is formed, and controlling the gas flow rate in a range of 4K sccm to 8K sccm, the pressure in a range of 600 mTorr to 1200 mTorr, the power in a range of 3 KW to 9 KW, and the treatment time in a range of 10 s to 60 s. ### Claim 7 (depends on 1) The method for manufacturing a thin film transistor according to claim 1, wherein the performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed comprises: performing the plasma bombardment treatment by using a gas mixture of N2O, O2, Ar, and N2 on the surface of the active layer on which the source/drain layer is formed, and controlling the gas flow rate in a range of 4K sccm to 8K sccm, the pressure in a range of 600 mTorr to 1200 mTorr, the power in a range of 3 KW to 9 KW, and the treatment time in a range of 10 s to 60 s. ### Claim 8 (depends on 1) The method for manufacturing a thin film transistor according to claim 1, wherein the plasma bombardment treatment on the surface of the active layer on which the source/drain layer is formed is performed in a chemical vapor deposition equipment or a dry etching equipment. ### Claim 9 (depends on 1) The method for manufacturing a thin film transistor according to claim 1, wherein the plasma bombardment treatment on the surface of the active layer on which the source/drain layer is formed is automatically controlled by a digital control technology. ### Claim 10 (depends on 1) The method for manufacturing a thin film transistor according to claim 1, wherein the plasma bombardment treatment on the surface of the active layer on which the source/drain layer is formed is performed in vacuum. ### Claim 11 (depends on 1) The method for manufacturing a thin film transistor according to claim 1, after performing the plasma bombardment treatment on the surface of the active layer on which the source/drain layer is formed, further comprising: disposing a protective layer on the active layer, on which the source/drain layer is formed, and on a top surface of the source/drain layer. ### Claim 12 (depends on 11) The method for manufacturing a thin film transistor according to claim 11, wherein the protective layer is formed by coating different types of photoresist on the active layer, on which the source/drain layer is formed, and on the top surface of the source/drain layer. ### Claim 13 (depends on 1) A thin film transistor, manufactured by using the method according to claim 1. ### Claim 14 (depends on 13) A display apparatus, comprising at least the thin film transistor according to claim 13. ### Claim 15 (depends on 2) The method for manufacturing a thin film transistor according to claim 2, wherein the performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed comprises: performing the plasma bombardment treatment by using one gas of N2O, O2, Ar, and N2 on the surface of the active layer on which the source/drain layer is formed, and controlling the gas flow rate in a range of 30K sccm to 70K sccm, the pressure in a range of 600 mTorr to 1200 mTorr, the power in a range of 4 KW to 12 KW, and the treatment time in a range of 10 s to 40 s. ### Claim 16 (depends on 2) The method for manufacturing a thin film transistor according to claim 2, wherein the performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed comprises: performing the plasma bombardment treatment by using two gases of N2O, O2, Ar, and N2 on the surface of the active layer on which the source/drain layer is formed, and controlling the gas flow rate in a range of 4K sccm to 8K sccm, the pressure in a range of 600 mTorr to 1200 mTorr, the power in a range of 3 KW to 9 KW, and the treatment time in a range of 10 s to 60 s. ### Claim 17 (depends on 2) The method for manufacturing a thin film transistor according to claim 2, wherein the performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed comprises: performing the plasma bombardment treatment by using three gases of N2O, O2, Ar, and N2 on the surface of the active layer on which the source/drain layer is formed, and controlling the gas flow rate in a range of 4K sccm to 8K sccm, the pressure in a range of 600 mTorr to 1200 mTorr, the power in a range of 3 KW to 9 KW, and the treatment time in a range of 10 s to 60 s. ### Claim 18 (depends on 2) The method for manufacturing a thin film transistor according to claim 2, wherein the performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed comprises: performing the plasma bombardment treatment by using a gas mixture of N2O, O2, Ar, and N2 on the surface of the active layer on which the source/drain layer is formed, and controlling the gas flow rate in a range of 4K sccm to 8K sccm, the pressure in a range of 600 mTorr to 1200 mTorr, the power in a range of 3 KW to 9 KW, and the treatment time in a range of 10 s to 60 s. ### Claim 19 (depends on 2) The method for manufacturing a thin film transistor according to claim 2, wherein the plasma bombardment treatment on the surface of the active layer on which the source/drain layer is formed is performed in a chemical vapor deposition equipment or a dry etching equipment. ### Claim 20 (depends on 2) The method for manufacturing a thin film transistor according to claim 2, wherein the plasma bombardment treatment on the surface of the active layer on which the source/drain layer is formed is automatically controlled by a digital control technology.