# US 2021/0082960 A1 · Integrated circuit device with improved layout > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082960 A1 - Document ID: US20210082960A1 - Status: Published application - Kind: A1 - Application number: 17/103,532 - Filed: 2020-11-24 - Published: 2021-03-18 - Earliest claimed: 2017-07-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Fong-yuan Chang; Chun-Chen Chen; Po-Hsiang Huang; Lee-Chung Lu; Chung-Te Lin; Jerry Chang Jui Kao; Sheng-Hsiung Chen; Chin-Chou Liu - Web page: https://patentgrep.com/patent/US20210082960A1 ## CPC - H10D 84/907: {CMOS gate arrays} - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - H10D 84/962: {Horizontal or vertical grid line density} - H10D 84/966: {Gate electrode terminals or contacts} - H10D 84/975: {Wiring regions or routing} - H10D 84/981: {Power supply lines} - H10D 84/985: {Two levels of metal} - H10D 89/10: Integrated device layouts - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1. ## Claims ### Claim 1 An integrated circuit device, comprising: a device layer having devices spaced in accordance with a predetermined device pitch; a first metal interconnection layer disposed above the device layer and coupled to the device layer; and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer, wherein the second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and wherein a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1. ### Claim 2 (depends on 1) The integrated circuit device of claim 1, wherein the ratio is X:Y where X and Y are integer values. ### Claim 3 (depends on 2) The integrated circuit device of claim 2, wherein X is 2 and Y is 3. ### Claim 4 (depends on 2) The integrated circuit device of claim 2, wherein X is 3 and Y is 5. ### Claim 5 (depends on 1) The integrated circuit device of claim 1, wherein the predetermined device pitch is a polysilicon line pitch. ### Claim 6 (depends on 1) The integrated circuit device of claim 1, wherein the integrated circuit device comprises a device corresponding to a cell, and the cell includes at least one cell connection pin in the first metal interconnection layer and at least one cell connection pin in the second metal interconnection layer. ### Claim 7 (depends on 6) The integrated circuit device of claim 6, further comprising a power strap formed in the second metal interconnection layer, wherein the cell is located under the power strap. ### Claim 8 (depends on 6) The integrated circuit device of claim 6, wherein the cell conforms with the equation M0_Enc≤(Max_M0_Length−Max_M1_Pitch_Length−VIA0_Width)/2, where: Max_M0_Length represents a maximum possible length of a line in the first metal interconnection layer in the cell; Max_M1_Pitch_Length represents a maximum possible pitch between two lines in the second metal interconnection layer in the cell; VIA0_Width represents a width of a via that connects a line in the first metal interconnection layer with a line in the second metal interconnection layer; and M0_Enc represents a distance from an outermost edge of the line in the first metal interconnection layer to an edge of a nearest possible via connecting the line in the first metal interconnection layer to the line in the second metal interconnection layer. ### Claim 9 (depends on 1) The integrated circuit device of claim 1, wherein the integrated circuit device includes first and second instances of a device, the first instance of the device corresponding with a first cell having a first cell layout and a second instance of the device corresponding with a second cell having a second cell layout, wherein the first and second cells have a same layout at the device layer and wherein the first and second device cells have corresponding metal lines in the second metal interconnection layer positioned differently with respect to a common identically located feature in the first and second cell layouts. ### Claim 10 (depends on 9) The integrated circuit device of the claim 9, wherein the integrated circuit device has predetermined track locations for metal lines in the second metal interconnection layer, and wherein the corresponding metal lines of the first and second cells are positioned differently to each align with a track location from the predetermined track locations. ### Claim 11 An integrated circuit device, comprising: a first instance of a device fabricated at a first location in accordance with a first cell layout; and a second instance of the device fabricated at a second location in accordance with a second cell layout; wherein the cell layouts includes a device layer, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer, wherein a ratio in the cell layouts of a predefined metal line pitch in the second metal interconnection layer to a predefined polysilicon line pitch in the device layer is less than 1, and wherein the first and second cell layouts differ in a relative location of at least one metal line in the second metal interconnection layer with respect to a common feature in the cell layouts. ### Claim 12 (depends on 11) The integrated circuit device of claim 11, wherein the locations of the at least one metal line in the second interconnection layer in the first and second cell layouts are laterally offset from one another with respect to the common feature in the cell layouts. ### Claim 13 (depends on 11) The integrated circuit device of claim 11, wherein the cell layouts include at least one connection pin in the second metal interconnection layer and at least one connection pin in the first metal interconnection layer. ### Claim 14 (depends on 11) The integrated circuit device of claim 11, wherein the cell layouts conform with the equation M0_Enc≤(Max_M0_Length−Max_M1_Pitch_Length−VIA0_Width)/2, where: Max_M0_Length represents a maximum possible length of a line in the first metal interconnection layer in the cell layouts; Max_M1_Pitch_Length represents a maximum possible pitch between two lines in the second metal interconnection layer in the cell layouts; VIA0_Width represents a width of a via that connects a line in the first metal interconnection layer with a line in the second metal interconnection layer; and M0_Enc represents a distance from an outermost edge of the line in the first metal interconnection layer to an edge of a nearest possible via connecting the line in the first metal interconnection layer to the line in the second metal interconnection layer. ### Claim 15 An integrated circuit device, comprising: a device layer having device features spaced in accordance with a predetermined pitch; a first interconnection layer disposed above the device layer and coupled to the device layer; and a second interconnection layer disposed above the first interconnection layer and coupled to the first interconnection layer through a first via layer, wherein the second interconnection layer has connection lines spaced in accordance with a predetermined line pitch, and wherein a ratio of the predetermined line pitch to predetermined device pitch is less than 1. ### Claim 16 (depends on 15) The integrated circuit of claim 15, wherein the predetermine pitch is a polysilicon line pitch. ### Claim 17 (depends on 15) The integrated circuit of claim 15, wherein the device features are gates. ### Claim 18 (depends on 15) The integrated circuit device of claim 15, wherein the integrated circuit device comprises a device corresponding to a cell, and the cell includes at least one cell connection pin in the first interconnection layer and at least one cell connection pin in the second interconnection layer. ### Claim 19 (depends on 18) The integrated circuit device of claim 18, further comprising a power strap formed in the second interconnection layer, wherein the cell is located under the power strap. ### Claim 20 (depends on 15) The integrated circuit device of claim 15, wherein the integrated circuit device includes first and second instances of a device, the first instance of the device corresponding with a first cell having a first cell layout and a second instance of the device corresponding with a second cell having a second cell layout, wherein the first and second cells have a same layout at the device layer and wherein the first and second device cells have corresponding interconnection lines in the second interconnection layer positioned differently with respect to a common identically located feature in the first and second cell layouts.