# US 2021/0082959 A1 · Semiconductor storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082959 A1 - Document ID: US20210082959A1 - Status: Published application - Kind: A1 - Application number: 17/008,236 - Filed: 2020-08-31 - Published: 2021-03-18 - Earliest claimed: 2019-09-17 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Sumiko DOMAE; Daisaburo TAKASHIMA - Web page: https://patentgrep.com/patent/US20210082959A1 ## CPC - G11C 11/2259: {Cell access} - H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels - G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 11/221: {using ferroelectric capacitors} - G11C 11/2255: {Bit-line or column circuits} - G11C 11/2273: {Reading or sensing circuits or methods} - G11C 11/2275: {Writing or programming circuits or methods} - H10B 51/40: characterised by the peripheral circuit region - H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 53/40: characterised by the peripheral circuit region - H10D 30/0415: {of FETs having ferroelectric gate insulators} - H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs} - H10B 53/10: characterised by the top-view layout - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers spaced apart from each other in a stacking direction. The columnar body penetrates the stacked body in the stacking direction. The columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers. ## Claims ### Claim 1 A semiconductor storage device comprising: a stacked body in which a plurality of first conductive layers are arranged to be spaced apart from each other in a stacking direction; and a columnar body that penetrates the stacked body in the stacking direction, wherein the columnar body includes: a columnar ferroelectric film; a semiconductor film disposed between the ferroelectric film and the first conductive layers; and an insulating film disposed between the semiconductor film and the first conductive layers. ### Claim 2 (depends on 1) The semiconductor storage device according to claim 1, wherein a memory chain is formed at a position where the plurality of first conductive layers and the columnar body intersect, the memory chain including a plurality of memory cells connected in series. ### Claim 3 (depends on 2) The semiconductor storage device according to claim 2, wherein the stacked body further includes a drive electrode film at a position higher than an upper end of the ferroelectric film, the semiconductor film and the insulating film of the columnar body extend to a height position of the drive electrode film, and a first select transistor is formed at a position where the drive electrode film and the columnar body intersect, the first select transistor being connected to one end of the memory chain. ### Claim 4 (depends on 3) The semiconductor storage device according to claim 3, wherein the stacked body further includes a lowermost first conductive layer at a position lower than a lower end of the ferroelectric film, the semiconductor film of the columnar body extends to a height position of the lowermost first conductive layer, and a second select transistor is formed at a position where the lowermost first conductive layer and the columnar body intersect, the second select transistor being connected to the other end of the memory chain. ### Claim 5 (depends on 2) The semiconductor storage device according to claim 2, wherein the memory cell is a one-transistor one-capacitor type memory cell. ### Claim 6 (depends on 5) The semiconductor storage device according to claim 5, wherein the memory cell includes a transistor and a ferroelectric capacitor connected in parallel between a first end of the memory cell and a second end of the memory cell. ### Claim 7 (depends on 1) The semiconductor storage device according to claim 1, further comprising: a second conductive layer connected to an upper end of the semiconductor film at a height position of an upper end of the columnar body; and a third conductive layer connected to a lower end of the semiconductor film at a height position of a lower end of the columnar body. ### Claim 8 A method of performing an operation to read data or write data in a semiconductor storage device that includes: a stacked body in which a plurality of conductive layers are arranged to be spaced apart from each other in a stacking direction; a columnar body that penetrates the stacked body in the stacking direction, wherein the columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers, wherein a plurality of memory cells connected in series is formed along the columnar body where the conductive layers intersect the columnar body; a bit line connected to the columnar body; and a plate line connected to the columnar body, said method comprising: applying different voltages to the bit line and the plate line to write first or second data into one of the memory cells. ### Claim 9 (depends on 8) The method according to claim 8, wherein the voltage applied to the bit line is lower than the voltage applied to the plate line when the first data is being written and the voltage applied to the bit line is higher than the voltage applied to the plate line when the second data is being written. ### Claim 10 (depends on 9) The method according to claim 9, wherein the voltage applied to the plate line when the first data is being written is different from the voltage applied to the plate line when the second data is being written. ### Claim 11 (depends on 9) The method according to claim 9, wherein the voltage applied to the plate line when the first data is being written is the same as the voltage applied to the plate line when the second data is being written. ### Claim 12 (depends on 8) The method according to claim 8, wherein when data is read from a memory cell, an operation to read the data from the memory cell is executed and then an operation to rewrite the data into the memory cell is executed. ### Claim 13 (depends on 8) The method according to claim 8, wherein the memory cells each include a transistor and a ferroelectric capacitor connected in parallel between a first end thereof and a second end thereof, and the ferroelectric capacitor stores a charge having a first polarity when the memory cell stores the first data and a charge having a second polarity when the memory cell stores the second data. ### Claim 14 (depends on 8) The method according to claim 8, further comprising: selecting one of the memory cells into which the first or second data is to be written, by applying a first voltage to the conductive layer connected to said one of the memory cells and applying a second voltage higher than the first voltage to the conductive layers connected other memory cells. ### Claim 15 A method of performing an operation to read data or write data in a semiconductor storage device that includes: a stacked body in which a plurality of conductive layers are arranged to be spaced apart from each other in a stacking direction; a columnar body that penetrates the stacked body in the stacking direction, wherein the columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers, wherein a plurality of memory cells connected in series is formed along the columnar body where the conductive layers intersect the columnar body; a bit line connected to the columnar body; a plate line connected to the columnar body; and a sense amplifier connected the bit line, said method comprising: selecting one of the memory cells to read; disconnecting the bit line from the sense amplifier to place the bit line in a floating state; while the bit line is in the floating state, applying a first voltage to the plate line to raise a voltage of the bit line; after the voltage of the bit line has been raised, connecting the bit line to the sense amplifier and comparing the voltage of the bit line against a reference voltage; and determining that data read from the selected memory cell is first data if the voltage of the bit line is less than the reference voltage and second data if the voltage of the bit line is greater than the reference voltage. ### Claim 16 (depends on 15) The method according to claim 15, further comprising: after said determining, while maintaining the connection between the bit line and the sense amplifier, lowering the voltage of the bit line to a second voltage if the first data is determined and raising the voltage of the bit line to a third voltage higher than the second voltage if the second data is determined. ### Claim 17 (depends on 16) The method according to claim 16, further comprising: maintaining the plate line at the first voltage when the bit line is connected to the sense amplifier and during said comparing and determining; and after said determining, while maintaining the connection between the bit line and the sense amplifier, applying the first voltage to the plate line during a first period to rewrite the first data in the memory cell and the third voltage to the plate line during a second period after the first period to rewrite the second data in the memory cell. ### Claim 18 (depends on 16) The method according to claim 16, further comprising: maintaining the plate line at the first voltage during an entire period the bit line is connected to the sense amplifier to rewrite the first data if the voltage of the bit line is lowered to the second voltage and to rewrite the second data if the voltage of the bit line is raised to the third voltage, wherein the first voltage is greater than the second voltage and less than the third voltage. ### Claim 19 (depends on 15) The method according to claim 15, wherein the memory cells each include a transistor and a ferroelectric capacitor connected in parallel between a first end thereof and a second end thereof, and the ferroelectric capacitor stores a charge having a first polarity when the memory cell stores the first data and a charge having a second polarity when the memory cell stores the second data. ### Claim 20 (depends on 15) The method according to claim 15, wherein one of the memory cells is selected for read by applying a second voltage to the conductive layer connected to said one of the memory cells and applying a third voltage higher than the second voltage to the conductive layers connected other memory cells.