# US 2021/0082955 A1 · Three-dimensional memory device containing ferroelectric memory elements encapsulated by transition metal-containing conductive elements and method of making thereof

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- Number: US 2021/0082955 A1
- Document ID: US20210082955A1
- Status: Published application
- Kind: A1
- Application number: 16/568,668
- Filed: 2019-09-12
- Published: 2021-03-18
- Earliest claimed: 2019-09-12
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Adarsh RAJASHEKHAR; Raghuveer S. MAKALA; Rahul SHARANGPANI; Seung-Yeul YANG; Fei ZHOU
- Web page: https://patentgrep.com/patent/US20210082955A1

## CPC

- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 64/033: {comprising ferroelectric layers}
- H10B 51/10: characterised by the top-view layout
- H10B 51/30: characterised by the memory core region
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.

## Claims

### Claim 1

A three-dimensional ferroelectric memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein each of the electrically conductive layers comprises a transition metal element-containing conductive liner and a conductive fill material portion;
a vertical semiconductor channel extending vertically through the alternating stack;
a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers; and
a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.

### Claim 2 (depends on 1)

The three-dimensional ferroelectric memory device of claim 1, wherein the ferroelectric material layer comprises:
an upper horizontally-extending portion that contacts a bottom surface of the respective overlying one of the insulating layers and a top surface of a respective electrically conductive layer;
a lower horizontally-extending portion that contacts a top surface of the respective underlying one of the insulating layers and a bottom surface of the respective electrically conductive layer; and
a tubular portion vertically extending between the upper horizontally-extending portion and the lower horizontally-extending portion, wherein the tubular portion laterally surrounds and contacts a respective one of the tubular transition metal element-containing conductive spacers.

### Claim 3 (depends on 1)

The three-dimensional ferroelectric memory device of claim 1, wherein each of the ferroelectric material layers has a cylindrical configuration and contacts an overlying one of the insulating layers an underlying one of the insulating layers.

### Claim 4 (depends on 1)

The three-dimensional ferroelectric memory device of claim 1, wherein the transition metal element-containing conductive liner comprises a transition metal element that is selected from iridium, ruthenium, palladium, osmium, rhenium, molybdenum or cobalt.

### Claim 5 (depends on 4)

The three-dimensional ferroelectric memory device of claim 4, wherein the transition metal element-containing conductive liner consists essentially of a conductive oxide of the transition metal element.

### Claim 6 (depends on 4)

The three-dimensional ferroelectric memory device of claim 4, wherein the transition metal element-containing conductive liner consists essentially of the transition metal element.

### Claim 7 (depends on 1)

The three-dimensional ferroelectric memory device of claim 1, wherein the tubular transition metal element-containing conductive spacers comprise a transition metal element that is selected from iridium, ruthenium, palladium, osmium, rhenium, molybdenum or cobalt.

### Claim 8 (depends on 7)

The three-dimensional ferroelectric memory device of claim 7, wherein the tubular transition metal element-containing conductive spacers consist essentially of a conductive oxide of the transition metal element.

### Claim 9 (depends on 7)

The three-dimensional ferroelectric memory device of claim 7, wherein the tubular transition metal element-containing conductive spacers consist essentially of the transition metal element.

### Claim 10 (depends on 1)

The three-dimensional ferroelectric memory device of claim 1, further comprising a tubular insulating spacer layer which contacts an inner sidewall of a respective one of the tubular transition metal element-containing conductive spacers and contacts a portion of an outer sidewall of the vertical semiconductor channel.

### Claim 11 (depends on 1)

The three-dimensional ferroelectric memory device of claim 1, further comprising a vertical stack of tubular insulating spacers, wherein each of the tubular insulating spacers contacts an inner sidewall of a respective one of the tubular transition metal element-containing conductive spacers and contacts a portion of an outer sidewall of the vertical semiconductor channel.

### Claim 12 (depends on 1)

The three-dimensional ferroelectric memory device of claim 1, wherein the vertical semiconductor channel has a straight outer sidewall that extends through each layer within the alternating stack and contacts a set of sidewalls of the insulating layers.

### Claim 13 (depends on 1)

The three-dimensional ferroelectric memory device of claim 1, wherein the vertical semiconductor channel has a laterally-undulating outer sidewall that includes laterally-protruding portions that protrude outward from vertical interfaces with the insulating layers toward a respective one of the electrically conductive layers.

### Claim 14

A method of forming a three-dimensional ferroelectric memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming memory openings vertically extending through the alternating stack;
forming a vertical semiconductor channel in each of the memory openings;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers;
forming a vertical stack of tubular transition metal element-containing conductive spacers around each of the memory openings prior to or after formation of the vertical semiconductor channels, wherein each of the tubular transition metal element-containing conductive spacers laterally surrounds a respective one of the vertical semiconductor channels;
forming a ferroelectric material layer in the backside recesses on the tubular transition metal element-containing conductive spacers; and
forming electrically conductive layers in the backside recesses by forming a transition metal element-containing conductive liner on the ferroelectric material layer, and forming a conductive fill material portion over the transition metal element-containing conductive liner.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
forming annular recesses by laterally recessing sidewalls of the sacrificial material layers selective to the insulating layers around each memory opening; and
forming the vertical stacks of tubular transition metal element-containing conductive spacers in the annular recesses.

### Claim 16 (depends on 15)

The method of claim 15, further comprising forming a tubular insulating spacer layer in the memory opening over the vertical stacks of tubular transition metal element-containing conductive spacers, wherein the vertical semiconductor channel is formed on the tubular insulating spacer layer.

### Claim 17 (depends on 14)

The method of claim 14, further comprising forming a vertical stack of tubular insulating spacers in the backside recesses around each of the vertical semiconductor channels.

### Claim 18 (depends on 17)

The method of claim 17, wherein the vertical stacks of tubular transition metal element-containing conductive spacers are formed in the backside recesses on physically exposed surfaces of the tubular insulating spacers.

### Claim 19 (depends on 14)

The method of claim 14, wherein the transition metal element-containing conductive liner comprises a metal liner comprising a transition metal element that is selected from iridium, ruthenium, palladium, osmium, rhenium, molybdenum or cobalt, or a metal oxide liner comprising an oxide of the transition metal element that is selected from iridium, ruthenium, palladium, osmium, rhenium, molybdenum or cobalt.

### Claim 20 (depends on 14)

The method of claim 14, wherein the tubular transition metal element-containing conductive spacers comprise metal spacers comprising a transition metal element that is selected from iridium, ruthenium, palladium, osmium, rhenium, molybdenum or cobalt, or metal oxide spacers comprising an oxide of the transition metal element that is selected from iridium, ruthenium, palladium, osmium, rhenium, molybdenum or cobalt.