# US 2021/0082953 A1 · Three-dimensional memory devices having through stair contacts and methods for forming the same

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- Number: US 2021/0082953 A1
- Document ID: US20210082953A1
- Status: Published application
- Kind: A1
- Application number: 17/097,635
- Filed: 2020-11-13
- Published: 2021-03-18
- Earliest claimed: 2019-01-02
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Qinxiang Wei; Jianhua Sun; Ji Xia
- Web page: https://patentgrep.com/patent/US20210082953A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10D 64/037: {comprising charge-trapping insulators}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10B 43/10: characterised by the top-view layout
- H10W 20/076: {in via holes or trenches}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a TSC. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack. The TSC extends vertically through the staircase structure of the memory stack. The TSC includes a conductor layer and a spacer circumscribing the conductor layer.

## Claims

### Claim 1

A three-dimensional (3D) memory device, comprising:
a memory stack comprising a plurality of interleaved conductive layers and dielectric layers, wherein edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack; and
a through stair contact (TSC) extending vertically through the staircase structure of the memory stack, wherein the TSC comprises a conductor layer and a spacer circumscribing the conductor layer.

### Claim 2 (depends on 1)

The 3D memory device of claim 1, wherein the conductive layers of the memory stack comprise polysilicon, and the dielectric layers of the memory stack comprise silicon oxide.

### Claim 3 (depends on 1)

The 3D memory device of claim 1, wherein the conductor layer of the TSC comprises a metal.

### Claim 4 (depends on 1)

The 3D memory device of claim 1, wherein the spacer of the TSC has a uniform thickness.

### Claim 5 (depends on 1)

The 3D memory device of claim 1, further comprising a channel structure extending vertically through an inner region of the memory stack, wherein the staircase structure is disposed in an outer region of the memory stack.

### Claim 6 (depends on 5)

The 3D memory device of claim 5, wherein the TSC is disposed inside the outer region of the memory stack.

### Claim 7 (depends on 5)

The 3D memory device of claim 5, wherein the TSC extends vertically through a smaller number of the conductive layers and dielectric layers of the memory stack than the channel structure.

### Claim 8 (depends on 1)

The 3D memory device of claim 1, wherein a cross-section of the TSC has a circular shape.

### Claim 9 (depends on 1)

The 3D memory device of claim 1, further comprising a peripheral device above or below the memory stack.

### Claim 10 (depends on 9)

The 3D memory device of claim 9, further comprising a first substrate on which the memory stack is formed, and a second substrate on which the peripheral device is formed.

### Claim 11 (depends on 10)

The 3D memory device of claim 10, further comprising an interlayer dielectric (ILD) layer between the first substrate and the memory stack.

### Claim 12 (depends on 10)

The 3D memory device of claim 10, wherein the first substrate comprises silicon, and the TSC is in contact with the first substrate.

### Claim 13 (depends on 1)

The 3D memory device of claim 1, further comprising a peripheral contact outside of the memory stack, wherein the peripheral contact comprises a conductor layer and a spacer circumscribing the conductor layer.

### Claim 14 (depends on 1)

The 3D memory device of claim 1, further comprising a word line contact in contact with one of the conductive layers of the memory stack at the staircase structure.

### Claim 15 (depends on 14)

The 3D memory device of claim 14, wherein a cross-section of the word line contact and a cross-section of the TSC have a same shape.

### Claim 16

A three-dimensional (3D) memory device, comprising:
a memory stack comprising a plurality of interleaved conductive layers and dielectric layers, wherein edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack;
a word line contact in contact with one of the conductive layers of the memory stack at the staircase structure; and
a through stair contact (TSC) extending vertically through the staircase structure of the memory stack, wherein a cross-section of the word line contact and a cross-section of the TSC have a same shape.

### Claim 17 (depends on 16)

The 3D memory device of claim 16, wherein the TSC comprises a conductor layer and a spacer circumscribing the conductor layer.

### Claim 18 (depends on 16)

The 3D memory device of claim 16, wherein the TSC and the word line contact each comprise a conductor layer having a same material.

### Claim 19

A three-dimensional (3D) memory device, comprising:
a memory stack comprising a plurality of interleaved conductive layers and dielectric layers, wherein edges of the interleaved conductive layers and dielectric layers define a staircase structure in an outer region of the memory stack;
a channel structure extending vertically through an inner region of the memory stack; and
a through stair contact (TSC) extending vertically through the staircase structure inside the outer region of the memory stack, wherein the TSC comprises a metal layer.

### Claim 20 (depends on 19)

The 3D memory device of claim 19, wherein the TSC comprises a spacer circumscribing the metal layer.