# US 2021/0082949 A1 · Semiconductor memory device and method for manufacturing semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082949 A1 - Document ID: US20210082949A1 - Status: Published application - Kind: A1 - Application number: 16/816,385 - Filed: 2020-03-12 - Published: 2021-03-18 - Earliest claimed: 2019-09-17 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hisashi HARADA; Ayaha HACHISUGA; Jun NISHIMURA; Wataru UNNO - Web page: https://patentgrep.com/patent/US20210082949A1 ## CPC - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/082: {the openings being tapered via holes} - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract According to one embodiment, a semiconductor memory device includes a first stacked body disposed between the belt-like portions and stacked a plurality of first conductive layers via a first insulating layer, a second stacked body disposed in a region in the first stacked body and stacked a plurality of second insulating layers via the first insulating layer, a first pillar extending in the first stacked body in a stacking direction of the first stacked body, and a plurality of second pillars extending in the stacking direction on both sides of the second stacked body facing the belt-like portions and arranged in the first direction, in which the second pillars each include a plate-like portion disposed at a height position of each of the first conductive layers, and the adjacent second pillars are connected to each other by the plate-like portion. ## Claims ### Claim 1 A semiconductor memory device comprising: a substrate; a plurality of belt-like portions arranged abreast to each other above the substrate and extending in a first direction along the substrate; a first stacked body disposed between the belt-like portions and stacked a plurality of first conductive layers via a first insulating layer; a second stacked body disposed in a region in the first stacked body and stacked a plurality of second insulating layers via the first insulating layer; a first pillar extending in the first stacked body in a stacking direction of the first stacked body and forming a memory cell at an intersection with at least a part of the first conductive layers; and a plurality of second pillars extending in the stacking direction on both sides of the second stacked body facing the belt-like portions and arranged in the first direction, wherein the second pillars each include a plate-like portion disposed at a height position of each of the first conductive layers, and the adjacent second pillars are connected to each other by the plate-like portion. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the first pillar is one of a plurality of first pillars, the first stacked body includes a memory region in which the first pillars are disposed, and the second stacked body is disposed in the memory region. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein a contact extending in the stacking direction is disposed in a region in the second stacked body. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, further comprising a second conductive layer disposed below the first conductive layers, wherein the first pillar has a lower end connected to the second conductive layer, and the contact penetrates the second conductive layer and has a lower end connected to lower wiring disposed between the substrate and the second conductive layer. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the second pillars are also arranged in a second direction intersecting the first direction, and the second stacked body is surrounded by the second pillars. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein the first pillar includes a memory layer disposed on an outer periphery of the first pillar, and the plate-like portion is made of a same material as at least a part of the memory layer. ### Claim 7 (depends on 6) The semiconductor memory device according to claim 6, wherein the first pillar is one of a plurality of first pillars, and a pitch of the first pillars and a pitch of the second pillars are substantially equal. ### Claim 8 (depends on 6) The semiconductor memory device according to claim 6, wherein a diameter of the first pillar and a diameter of each of the second pillars are substantially equal at a height position of the first insulating layer. ### Claim 9 (depends on 1) The semiconductor memory device according to claim 1, further comprising a columnar portion extending in the first stacked body in the stacking direction of the first stacked body and filled with a third insulating layer, wherein the plate-like portion is made of a same material as the third insulating layer. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, wherein the columnar portion is one of a plurality of columnar portions, and a pitch of the columnar portions and a pitch of the second pillars are substantially equal. ### Claim 11 (depends on 9) The semiconductor memory device according to claim 9, wherein a diameter of the columnar portion and a diameter of each of the second pillars are substantially equal at a height position of the first insulating layer. ### Claim 12 (depends on 1) The semiconductor memory device according to claim 1, wherein the plate-like portion extends concentrically from a side surface of each of the second pillars, except for portions connected to each other. ### Claim 13 (depends on 1) The semiconductor memory device according to claim 1, wherein the first insulating layer is continuously formed over a region in the second stacked body and a region of the first stacked body on both sides of the second stacked body through the adjacent second pillars. ### Claim 14 (depends on 1) The semiconductor memory device according to claim 1, wherein each of the first conductive layers in the first stacked body has an edge facing the second pillars and having a shape formed by connecting a plurality of arcs. ### Claim 15 A method for manufacturing a semiconductor memory device, the semiconductor memory device comprising: a first stacked body stacked a plurality of conductive layers via a first insulating layer above a substrate; a second stacked body disposed in a region in the first stacked body and stacked a plurality of second insulating layers via the first insulating layer; and a first pillar extending in the first stacked body in a stacking direction of the first stacked body and forming a memory cell at an intersection with at least a part of the conductive layers, and the method comprising: forming a plurality of first through holes extending in a boundary portion between a first region and a second region of a third stacked body in the stacking direction and arranged in two rows in a first direction along the substrate, the third stacked body being stacked the second insulating layers via the first insulating layer, and the first stacked body being to be formed in the first region of the third stacked body by replacing the second insulating layers of the first region with the conductive layers and the second stacked body being to be formed in the second region of the third stacked body by inhibiting replacement of the second insulating layers of the second region with the conductive layers; receding the second insulating layers from inner wall surfaces of the first through holes to remove the second insulating layers between the first through holes adjacent in the same row; covering the inner wall surfaces of the first through holes with a third insulating layer and filling, with the third insulating layer, a gap from which the second insulating layers have been removed to form a plurality of second pillars connected to each other in the same row by the third insulating layer; forming, outside an arrangement of the second pillars in two rows, a groove extending in the third stacked body in the stacking direction and facing the arrangement of the second pillars; and replacing, with the conductive layers, the second insulating layers between the second pillars and the groove without replacing the second insulating layers inside the arrangement of the second pillars in two rows. ### Claim 16 (depends on 15) The method for manufacturing the semiconductor memory device according to claim 15, further comprising forming a contact extending in a region in the second stacked body in the stacking direction. ### Claim 17 (depends on 15) The method for manufacturing the semiconductor memory device according to claim 15, further comprising: arranging the second pillars in a second direction intersecting the first direction, the second stacked body being formed in a region surrounded by the second pillars. ### Claim 18 (depends on 15) The method for manufacturing the semiconductor memory device according to claim 15, further comprising: forming a second through hole extending in the third stacked body in the stacking direction and covering an inner wall surface of the second through hole with a memory layer and covering the memory layer with a channel layer to form the first pillar in the first region, wherein the inner wall surfaces of the first through holes are covered with the third insulating layer made of a same material as at least a part of the memory layer in parallel with covering the inner wall surface of the second through hole with the memory layer. ### Claim 19 (depends on 15) The method for manufacturing the semiconductor memory device according to claim 15, further comprising: forming a third through hole extending in the third stacked body in the stacking direction and filling the third through hole with the third insulating layer to form a columnar portion in the first region, wherein the inner wall surfaces of the first through holes are covered with the third insulating layer in parallel with filling the third through hole with the third insulating layer. ### Claim 20 (depends on 15) The method for manufacturing the semiconductor memory device according to claim 15, wherein, the second insulating layers are concentrically receded from the inner wall surfaces of the first through holes by isotropic etching the second insulating layers between the first through holes adjacent in the same row.