# US 2021/0082945 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082945 A1 - Document ID: US20210082945A1 - Status: Published application - Kind: A1 - Application number: 17/005,514 - Filed: 2020-08-28 - Published: 2021-03-18 - Earliest claimed: 2019-09-17 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Kiyomitsu YOSHIDA - Web page: https://patentgrep.com/patent/US20210082945A1 ## CPC - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/10: characterised by the top-view layout - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10W 20/0693: {by forming self-aligned vias} - H10W 20/076: {in via holes or trenches} - H10W 20/082: {the openings being tapered via holes} - H10W 20/083: {the openings being via holes penetrating underlying conductors} - H10W 20/42: Vias, e.g. via plugs - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract According to one embodiment, a semiconductor memory device includes a first insulating layer; a first conductive layer provided in the first insulating layer and extending in the first direction; a second conductive layer extending in the first direction and provided adjacent to the first conductive layer in a second direction; and a contact plug coupled to one surface of the first conductive layer in a third direction. Thicknesses in the third direction of portions of the first and second conductive layers that overlap the contact plug in the third direction are smaller than thicknesses in the third direction of portions of the first and second conductive layers that do not overlap the contact plug in the third direction. ## Claims ### Claim 1 A semiconductor memory device comprising: a first insulating layer; a first conductive layer provided in the first insulating layer and extending in the first direction; a second conductive layer extending in the first direction and provided adjacent to the first conductive layer in a second direction intersecting the first direction; and a contact plug coupled to one surface of the first conductive layer in a third direction intersecting the first and second directions, wherein thicknesses in the third direction of portions of the first and second conductive layers that overlap the contact plug in the third direction are smaller than thicknesses in the third direction of portions of the first and second conductive layers that do not overlap the contact plug in the third direction. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a third conductive layer provided in the first insulating layer, extending in the first direction, and provided adjacent to the second conductive layer on a side opposite to the first conductive layer with respect to the second conductive layer in the second direction, wherein the thicknesses in the third direction of the portions of the first and second conductive layers that overlap the contact plug in the third direction are smaller than the thickness in the third direction of the third conductive layer. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the contact plug has a pillar shape extending in the third direction, and a first cross-sectional area taken along the first and second directions of a first portion of the contact plug is smaller than a second cross-sectional area taken along the first and second directions of a second portion of the contact plug, the first portion of the contact plug being close to the first conductive layer, the second portion of the contact plug being far from the first conductive layer, compared to the first cross-sectional area. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a fourth conductive layer provided in the first insulating layer, extending in the first direction, and provided on a side opposite to the second conductive layer with respect to the first conductive layer in the second direction, wherein a thickness in the third direction of a portion of the fourth conductive layer that overlaps the contact plug in the third direction is smaller than thicknesses in the third direction of portions of the first and second conductive layers that do not overlap the contact plug in the third direction. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a second insulating layer provided between the second conductive layer and the contact plug. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a plurality of fifth conductive layers stacked in the third direction and provided on a side of another surface of the first conductive layer opposite to said one surface of the first conductive layer on a side of the contact plug in the third direction; and a pillar penetrating the fifth conductive layers in the third direction, and electrically coupled to the first conductive layer. ### Claim 7 (depends on 6) The semiconductor memory device according to claim 6, wherein a portion at which each of the fifth conductive layers and the pillar intersect functions as a memory cell transistor. ### Claim 8 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a first circuit provided on a side opposite to the first conductive layer with respect to the contact plug in the third direction, and electrically coupled to the contact plug; and a substrate which is provided on a side opposite to the contact plug with respect to the first circuit in the third direction and in which the first circuit is formed. ### Claim 9 A semiconductor memory device comprising: a first insulating layer; a first conductive layer provided in the first insulating layer and extending in the first direction; a first contact plug coupled to one surface of the first conductive layer in a second direction intersecting the first direction; and a second contact plug provided on a side of one surface of the first conductive layer in the second direction, wherein a first thickness in the second direction of a portion of the first conductive layer that overlaps the first contact plug in the second direction is smaller than a second thickness in the second direction of a portion of the first conductive layer that does not overlap the first and second contact plugs in the second direction, and a third thickness in the second direction of a portion of the first conductive layer that overlaps the second contact plug in the second direction is smaller than the second thickness. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, further comprising: a second conductive layer provided in the first insulating layer, extending in the first direction, and provided adjacent to the first conductive layer in a third direction intersecting the first and second directions, wherein a thickness in the second direction of a portion of the second conductive layer that overlaps the first contact plug in the second direction is smaller than a thickness in the second direction of a portion of the second conductive layer that does not overlap the first contact plug in the second direction. ### Claim 11 (depends on 9) The semiconductor memory device according to claim 9, wherein the first contact plug has a pillar shape extending in the second direction, and a first cross-sectional area taken along the first direction and a third direction intersecting the first and second directions of a first portion of the first contact plug is smaller than a second cross-sectional area taken along the first and third directions of a second portion of the first contact plug, the first portion of the first contact plug being close to the first conductive layer, the second portion of the first contact plug being far from the first conductive layer, compared to the first cross-sectional area. ### Claim 12 (depends on 10) The semiconductor memory device according to claim 10, further comprising: a third conductive layer provided in the first insulating layer, extending in the first direction, and provided on a side opposite to the second conductive layer with respect to the first conductive layer in the third direction, wherein a thickness in the second direction of a portion of the third conductive layer that overlaps the first contact plug in the second direction is smaller than a thickness in the second direction of a portion of the third conductive layer that does not overlap the first contact plug in the second direction. ### Claim 13 (depends on 10) The semiconductor memory device according to claim 10, further comprising: a second insulating layer provided between the second conductive layer and the first contact plug. ### Claim 14 (depends on 9) The semiconductor memory device according to claim 9, further comprising: a plurality of fourth conductive layers stacked in the second direction and provided on a side of another surface of the first conductive layer opposite to said one surface on a side of the first contact plug in the second direction; and a pillar penetrating the fourth conductive layers in the second direction, and electrically coupled to the first conductive layer. ### Claim 15 (depends on 14) The semiconductor memory device according to claim 14, wherein a portion at which each of the fourth conductive layers and the pillar intersect functions as a memory cell transistor. ### Claim 16 (depends on 9) The semiconductor memory device according to claim 9, further comprising: a first circuit provided on a side opposite to the first conductive layer with respect to the first contact plug in the second direction, and electrically coupled to the contact plug; and a substrate which is provided on a side opposite to the first contact plug with respect to the first circuit in the second direction and in which the first circuit is formed. ### Claim 17 A manufacturing method of a semiconductor memory device, comprising: forming, in a first insulating layer, a first conductive layer and a second conductive layer extending in the first direction and aligned in a second direction intersecting the first direction; forming a second insulating layer on the first insulating layer and on the first and second conductive layers; removing a portion of the second insulating layer that is on the first and second conductive layers and exposing the first and second conductive layers; removing the exposed first and second conductive layers to a first depth; forming a third insulating layer on the first and second conductive layers that have been removed to the first depth; forming a fourth insulating layer on the third insulating layer; removing a portion of the fourth insulating layer that is above the first and second conductive layers and exposing a portion of the third insulating layer that is on the first and second conductive layers; removing a portion of the third insulating layer that is on the first conductive layer and exposing the first conductive layer; and forming a third conductive layer on the exposed first conductive layer. ### Claim 18 (depends on 17) The manufacturing method of the semiconductor memory device according to claim 17, wherein removing the portion of the third insulating layer that is on the first conductive layer includes maintaining the third insulating layer on the second conductive layer. ### Claim 19 (depends on 17) The manufacturing method of the semiconductor memory device according to claim 17, further comprising forming a conductive pad on the third conductive layer. ### Claim 20 (depends on 17) The manufacturing method of the semiconductor memory device according to claim 17, further comprising: stacking a plurality of fourth conductive layers in a third direction intersecting the first and second directions between a substrate and the first and second conductive layers; and forming a pillar penetrating the fourth conductive layers in the third direction and electrically coupled to the first conductive layer.