# US 2021/0082943 A1 · Semiconductor memory device and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082943 A1 - Document ID: US20210082943A1 - Status: Published application - Kind: A1 - Application number: 16/797,285 - Filed: 2020-02-21 - Published: 2021-03-18 - Earliest claimed: 2019-09-12 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Kyungmin Jang - Web page: https://patentgrep.com/patent/US20210082943A1 ## CPC - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/40: characterised by the peripheral circuit region - H10P 14/6329: {using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition} - H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)} - H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz} - H10B: ELECTRONIC MEMORY DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract According to an embodiment, a semiconductor memory device includes a semiconductor substrate, a control circuit arranged on the semiconductor substrate, and a memory cell array arranged above the control circuit. The memory cell array includes a plurality of three-dimensionally-arranged memory cells, and is controlled by the control circuit. A first nitride layer is arranged between the control circuit and the memory cell array, and a second nitride layer is arranged between the control circuit and the first nitride layer. ## Claims ### Claim 1 A semiconductor memory device, comprising: a semiconductor substrate; a control circuit arranged on the semiconductor substrate; a memory cell array arranged above the control circuit, including a plurality of three-dimensionally-arranged memory cells, and controlled by the control circuit; a first nitride layer arranged between the control circuit and the memory cell array; and a second nitride layer arranged between the control circuit and the first nitride layer. ### Claim 2 (depends on 1) The device according to claim 1, wherein a content of hydrogen in the second nitride layer is lower than a content of hydrogen in the first nitride layer. ### Claim 3 (depends on 1) The device according to claim 1, wherein a density of the second nitride layer is lower than a density of the first nitride layer. ### Claim 4 (depends on 1) The device according to claim 1, wherein an etching rate of the second nitride layer is greater than an etching rate of the first nitride layer. ### Claim 5 (depends on 1) The device according to claim 1, wherein the memory cell array comprises: a plurality of first conductive layers arranged at intervals in a first direction; a pillar extending through the first conductive layers in the first direction and including a semiconductor layer; and a second conductive layer arranged below a bottommost one of the first conductive layers so as to be in contact with the semiconductor layer. ### Claim 6 (depends on 5) The device according to claim 5, further comprising: a conductor extending through the second nitride layer, the first nitride layer, and the first conductive layers in the first direction. ### Claim 7 (depends on 1) The device according to claim 1, wherein the control circuit includes a MOS transistor, and the MOS transistor includes boron-containing polycrystalline silicon. ### Claim 8 (depends on 1) The device according to claim 1, wherein the memory cell array comprises a plurality of first conductive layers arranged at intervals in a first direction, and both of areas of respective cross sections of the first nitride layer and the second nitride layer cut along planes intersecting the first direction are greater than an area of a cross section of each of the first conducive layers cut along a plane intersecting the first direction. ### Claim 9 (depends on 1) The device according to claim 1, wherein the device is a NAND flash memory. ### Claim 10 A semiconductor memory device, comprising: a semiconductor substrate; a transistor on the semiconductor substrate; a layer stack above the transistor, the layer stack including a plurality of conductive layers arranged at intervals in a first direction, a semiconductor layer that passes through the conductive layers in the first direction, and a charge storage layer between the semiconductor layer and the conductive layers; a first nitride layer between the transistor and the layer stack; and a second nitride layer between the transistor and the first nitride layer, the second nitride layer being different from the first nitride layer. ### Claim 11 A method of manufacturing a semiconductor memory device, comprising: forming a transistor on a semiconductor substrate; forming a first nitride layer and a second nitride layer different from the first nitride layer above the transistor; and forming a layer stack above the first nitride layer and the second nitride layer, the layer stack including a plurality of conductive layers arranged at intervals in a first direction, a semiconductor layer that passes through the conductive layers in the first direction, and a charge storage layer between the semiconductor layer and the conductive layers. ### Claim 12 (depends on 11) The method according to claim 11, wherein the second nitride layer is between the first nitride layer and the transistor, and the second nitride layer is formed by physical vapor deposition, and the first nitride layer is formed by chemical vapor deposition. ### Claim 13 (depends on 11) The method according to claim 11, wherein forming the layer stack comprises: alternately stacking first insulating layers and second insulating layers above the first nitride layer and the second nitride layer; and replacing the second insulating layers with the conductive layers, wherein the second insulating layers contain a nitride, and are formed by chemical vapor deposition. ### Claim 14 (depends on 11) The method according to claim 11, further comprising: forming a conductor after the formation of the layer stack, wherein the conductor extends through the second nitride layer, the first nitride layer, and the conductive layers in the first direction, and reaches the transistor. ### Claim 15 (depends on 11) The method according to claim 11, wherein the transistor includes boron-containing polycrytalline silicon. ### Claim 16 (depends on 11) The method according to claim 11, wherein the second nitride layer is between the first nitride layer and the transistor, and a content of hydrogen in the second nitride layer is lower than a content of hydrogen in the first nitride layer. ### Claim 17 (depends on 11) The method according to claim 11, wherein the second nitride layer is between the first nitride layer and the transistor, and a density of the second nitride layer is lower than a density of the first nitride layer. ### Claim 18 (depends on 11) The method according to claim 11, wherein the second nitride layer is between the first nitride layer and the transistor, and an etching rate of the second nitride layer is greater than an etching rate of the first nitride layer.