# US 2021/0082942 A1 · Semiconductor memory device and method for manufacturing same

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- Number: US 2021/0082942 A1
- Document ID: US20210082942A1
- Status: Published application
- Kind: A1
- Application number: 17/106,414
- Filed: 2020-11-30
- Published: 2021-03-18
- Earliest claimed: 2014-09-12
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Yoshiaki FUKUZUMI; Hideaki AOCHI
- Web page: https://patentgrep.com/patent/US20210082942A1

## CPC

- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/30: characterised by the memory core region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10P 10/12: {Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates (preparing SOI wafers using bonding H10P90/1914)}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/701: {characterised by the pads after the direct bonding}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

## Claims

### Claim 1

A semiconductor memory device comprising:
an array chip including a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells and not including a substrate;
a circuit chip including a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit, the circuit chip being stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer;
a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer;
a pad provided in the array chip; and
an external connection electrode reaching the pad from a surface side of the array chip.