# US 2021/0082940 A1 · Memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082940 A1 - Document ID: US20210082940A1 - Status: Published application - Kind: A1 - Application number: 17/106,667 - Filed: 2020-11-30 - Published: 2021-03-18 - Earliest claimed: 2018-06-19 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Yasuhiro UCHIMURA; Tatsufumi HAMADA; Shinichi SOTOME; Tomohiro KUKI; Yasunori OSHIMA; Osamu ARISUMI - Web page: https://patentgrep.com/patent/US20210082940A1 ## CPC - H10B 43/10: characterised by the top-view layout - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10D 64/037: {comprising charge-trapping insulators} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract According to one embodiment, a memory device includes a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate. The semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate. The first portion has a thickness larger than a thickness of the second portion. ## Claims ### Claim 1 A memory device comprising: a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate, wherein the semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate, and the first portion of the semiconductor layer has a thickness larger than a thickness of the second portion of the semiconductor layer. ### Claim 2 (depends on 1) The memory device according to claim 1, wherein the semiconductor layer includes a third portion between the second portion of the semiconductor layer and the substrate, and the third portion of the semiconductor layer has a thickness smaller than a thickness of the second portion of the semiconductor layer. ### Claim 3 (depends on 1) The memory device according to claim 1, wherein the first portion of the semiconductor layer has an impurity concentration higher than an impurity concentration of the second portion of the semiconductor layer. ### Claim 4 (depends on 1) The memory device according to claim 1, wherein the first portion of the semiconductor layer is an amorphous layer or a microcrystalline layer, and the second portion of the semiconductor layer is a polycrystalline layer. ### Claim 5 (depends on 2) The memory device according to claim 2, wherein the first portion of the semiconductor layer includes at least one selected from boron (B), carbon (C), germanium (Ge), argon (Ar), xenon (Xe), fluorine (F), and BF2. ### Claim 6 (depends on 2) The memory device according to claim 2, wherein the first portion of the semiconductor layer has a grain size smaller than a grain size of the second portion of the semiconductor layer. ### Claim 7 (depends on 1) The memory device according to claim 1, wherein the first portion of the semiconductor layer and the second portion of the semiconductor layer are polycrystalline layers. ### Claim 8 (depends on 7) The memory device according to claim 7, wherein the first portion of the semiconductor layer includes at least one selected from boron (B), phosphorus (P), argon (Ar), and BF2. ### Claim 9 (depends on 7) The memory device according to claim 7, wherein the first portion of the semiconductor layer has a grain size larger than a grain size of the second portion. ### Claim 10 (depends on 1) The memory device according to claim 1, wherein the pillar includes a core layer and an air gap, the air gap is arranged inside the core layer, and a top end of the air gap with respect to the direction perpendicular to the surface of the substrate is positioned on a side of the substrate with respect to the first portion of the semiconductor layer. ### Claim 11 A memory device, comprising: a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure, the pillar including: a core layer; a semiconductor layer extending in a direction perpendicular to a surface of the substrate and including a first portion on a side of an upper portion of the structure, and a second portion in contact with an outer surface of the core layer between the first portion of the semiconductor layer and the substrate; and a reformed layer having a lower end in contact with the first portion of the semiconductor layer. ### Claim 12 (depends on 11) The memory device according to claim 11, wherein the reformed layer includes at least one selected from a nitride, oxide, and carbide of silicon. ### Claim 13 (depends on 11) The memory device according to claim 11, wherein the first portion of the semiconductor layer includes a third portion below the reformed layer and a fourth portion above the third portion of the semiconductor layer, and the reformed layer includes an inner side surface in contact with the fourth portion of the semiconductor layer. ### Claim 14 (depends on 11) The memory device according to claim 11, wherein the reformed layer includes an outer side surface in contact with the first portion of the semiconductor layer. ### Claim 15 (depends on 11) The memory device according to claim 11, wherein the pillar further includes a memory layer extending in the direction perpendicular to the surface of the substrate, and the reformed layer includes an outer side surface in contact with the memory layer. ### Claim 16 (depends on 11) The memory device according to claim 11, wherein the reformed layer has a cylindrical or annular shape. ### Claim 17 (depends on 11) The memory device according to claim 11, wherein the pillar at an upper end of the first portion of the semiconductor layer has a diameter smaller than a diameter of the pillar at a lower end of the first portion of the semiconductor layer. ### Claim 18 (depends on 11) The memory device according to claim 11, wherein the first portion of the semiconductor layer has a reverse tapered shape. ### Claim 19 (depends on 11) The memory device according to claim 11, wherein the pillar includes an air gap arranged inside the core layer, and a top end of the air gap in the direction perpendicular to the surface of the substrate is positioned on a side of the substrate with respect to the first portion of the semiconductor layer.