# US 2021/0082938 A1 · Single poly non-volatile memory device, method of manufacturing the same and single poly non-volatile memory device array

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- Number: US 2021/0082938 A1
- Document ID: US20210082938A1
- Status: Published application
- Kind: A1
- Application number: 17/108,444
- Filed: 2020-12-01
- Published: 2021-03-18
- Earliest claimed: 2016-01-15
- Assignees: Key Foundry Co., Ltd.
- Applicants: Key Foundry Co., Ltd.
- Inventors: Su Jin KIM; Hye Jin YOO
- Web page: https://patentgrep.com/patent/US20210082938A1

## CPC

- H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- G11C 2216/10: Floating gate memory cells with a single polysilicon layer
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.

## Claims

### Claim 1

An array of non-volatile memory cells, each memory cell comprising:
a selection transistor comprising a source electrode and a selection gate electrode;
a sensing transistor comprising a drain electrode and a sensing gate;
a control gate electrode disposed adjacent to a control gate;
a source line coupled to the source electrode of the selection transistor for receiving a source voltage;
a selection gate line coupled to the selection gate electrode of the selection transistor for receiving a selection gate voltage;
a bit line coupled to the drain electrode of the sensing transistor for receiving a drain voltage;
a control gate line coupled to the control gate electrode for receiving a control gate voltage; and
a floating gate connected to the control gate and the sensing gate,
wherein the floating gate is configured to charge or discharge electric charges according to a voltage applied to the control gate electrode and the source electrode.

### Claim 2 (depends on 1)

The array of claim 1, wherein a positive program voltage and a negative program voltage are applied to the control gate electrode and the source electrode, respectively, for a program operation, such that electrons are injected into the sensing transistor according to a voltage difference between the control gate electrode and the source electrode.

### Claim 3 (depends on 1)

The array of claim 1, wherein a negative program voltage and a positive program voltage are applied to the control gate electrode and the source electrode, respectively, for an erase operation, such that the sensing transistor discharges electrons according to a voltage difference between the control gate electrode and the source electrode.

### Claim 4 (depends on 1)

The array of claim 1, wherein when a potential between the control gate electrode and the source electrode corresponds to a positive voltage, the non-volatile memory cell injects electrons into the sensing gate for a program operation, and
wherein when a potential between the control gate electrode and the source electrode corresponds to a negative voltage, the non-volatile memory cell discharges electrons of the sensing gate for an erase operation.

### Claim 5 (depends on 1)

The array of claim 1, wherein each memory cell further comprises:
a first well disposed in a substrate, such that the selection transistor and the sensing transistor are disposed on the first well; and
a second well disposed spaced apart from the first well by an insulating layer and having a same conductivity type as the first well, such that the control gate electrode is disposed on the second well.

### Claim 6 (depends on 1)

The array of claim 1, wherein the control gate is disposed between the floating gate and the control gate electrode.

### Claim 7 (depends on 5)

The array of claim 5, wherein the sensing gate of the sensing transistor is formed at an upper portion of the first well, and
wherein the control gate is formed at an upper portion of the second well.

### Claim 8 (depends on 5)

The array of claim 5, wherein the selection transistor further comprises:
a first diffusion area formed in the first well;
a source region formed adjacent to the first diffusion area and having a conductivity type opposite to that of the first diffusion area, wherein the source electrode is coupled to the first diffusion area and the source region, such that the source voltage is applied to the selection transistor and the sensing transistor through the first well;
a drain region formed in the first well; and
a selection gate coupled to the selection gate electrode.

### Claim 9 (depends on 8)

The array of claim 8, wherein the sensing transistor further comprises a source region formed in the first well,
wherein the source region of the sensing transistor shares the drain region of the selection transistor, and no electrodes are connected to the source region of the sensing transistor and the drain region of the selection transistor.

### Claim 10 (depends on 8)

The array of claim 8, wherein each memory cell further comprises:
a second diffusion area formed in the second well and having a same conductivity type as the second well, such that the control gate electrode is connected to the second diffusion area.

### Claim 11 (depends on 1)

The array of claim 1, wherein a plurality of non-volatile memory cells are connected to each other in parallel to form the array of the non-volatile memory cells.

### Claim 12

An array of non-volatile memory cells, the array comprising:
a first non-volatile memory cell array comprising:
a first selection transistor comprising a first source electrode and a first selection gate electrode;
a first sensing transistor comprising a first drain electrode and a first sensing gate;
a first control gate electrode disposed adjacent to a first control gate; and
a first floating gate connected to the first sensing gate and the first control gate, and
a second non-volatile memory cell array comprising:
a second selection transistor comprising a second source electrode and a second selection gate electrode;
a second sensing transistor comprising a second drain electrode; and
a second control gate electrode disposed adjacent to a second control gate;
a first source line coupled to the first source electrode of the first selection transistor and the second source electrode of the second selection transistor;
a first bit line coupled to the first drain electrode of the first sensing transistor and the second drain electrode of the second sensing transistor;
a first selection gate line coupled to the first selection gate electrode of the first selection transistor; and
a first control gate line coupled to the first control gate electrode.

### Claim 13 (depends on 12)

The array of claim 12, further comprising:
a second selection gate line coupled to the second selection gate electrode of the second selection transistor; and
a second control gate line coupled to the second control gate electrode.

### Claim 14 (depends on 12)

The array of claim 12, wherein the first non-volatile memory cell array further comprises:
a first well disposed in a substrate, such that the first selection transistor and the first sensing transistor are formed on the first well; and
a second well disposed spaced apart from the first well by an insulating layer, and having a same conductivity type as the first well, such that the first control gate electrode is disposed on the second well.

### Claim 15 (depends on 12)

The array of claim 12, wherein a drain region of the first selection transistor shares a source region of the first sensing transistor.

### Claim 16 (depends on 14)

The array of claim 14, wherein a first portion of the first floating gate is formed at an upper portion of the first well, and a second portion of the first floating gate is formed at an upper portion of the second well.

### Claim 17 (depends on 14)

The array of claim 14, wherein the first non-volatile memory cell array further comprises:
a first diffusion area formed in the first well;
a source region formed adjacent to the first diffusion area and having a conductivity type opposite to that of the first diffusion area, wherein the first source electrode is coupled to the first diffusion area and the source region, such that a source voltage is applied to the first selection transistor and the first sensing transistor through the first well;
a drain region formed in the first well; and
a second diffusion area formed in the second well and having a same conductivity type as the second well, such that the first control gate electrode is connected to the second diffusion area.

### Claim 18 (depends on 12)

The array of claim 12, wherein the first source line is arranged parallel to the first bit line, and the first selection gate line is arranged parallel to the first control gate line, and
wherein each of the first source line and the first bit line is arranged vertically to the first selection gate line and the first control gate line.