# US 2021/0082933 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082933 A1 - Document ID: US20210082933A1 - Status: Published application - Kind: A1 - Application number: 16/798,577 - Filed: 2020-02-24 - Published: 2021-03-18 - Earliest claimed: 2019-09-17 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Takamasa ITO - Web page: https://patentgrep.com/patent/US20210082933A1 ## CPC - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract According to an embodiment, a semiconductor memory device includes a first conductive layer and second conductive layers arranged at intervals in a first direction above the first conductive layer. A semiconductor layer extends in the first direction in the second conductive layers to be in contact with the first conductive layer. A charge storage layer is between the semiconductor layer and the second conductive layers. A metal layer extends in the first direction and a second direction above the first conductive layer, and separates the second conductive layers. The device further includes an insulating layer. The insulating layer includes a portion between the metal layer and the first conductive layer and a portion between the metal layer and the second conductive layers. ## Claims ### Claim 1 A semiconductor memory device, comprising: a first conductive layer; a plurality of second conductive layers arranged at intervals in a first direction above the first conductive layer; a first semiconductor layer extending in the first direction in the second conductive layers so as to be in contact with the first conductive layer; a charge storage layer arranged between the first semiconductor layer and the second conductive layers; a metal layer extending in the first direction and a second direction intersecting the first direction above the first conductive layer, and separating the second conductive layers in a third direction intersecting the first direction and the second direction; and a first insulating layer including a first portion arranged between the metal layer and the first conductive layer and a second portion arranged between the metal layer and the second conductive layers. ### Claim 2 (depends on 1) The device according to claim 1, wherein the metal layer is insulated from the first conductive layer by the first insulating layer. ### Claim 3 (depends on 1) The device according to claim 1, wherein the first insulating layer covers the metal layer in the first conductive layer. ### Claim 4 (depends on 1) The device according to claim 1, wherein an entirety of a portion of the metal layer in the first conductive layer faces the first conductive layer via the first insulating layer. ### Claim 5 (depends on 1) The device according to claim 1, wherein the metal layer contains tungsten. ### Claim 6 (depends on 1) The device according to claim 1, wherein the metal layer contains titanium nitride. ### Claim 7 (depends on 1) The device according to claim 1, wherein the metal layer contains titanium and titanium nitride. ### Claim 8 (depends on 1) The device according to claim 1, further comprising: a second semiconductor layer extending in the first direction, wherein the metal layer is arranged between the first insulating layer and the second semiconductor layer. ### Claim 9 (depends on 1) The device according to claim 1, wherein a lower end of the first insulating layer is below an upper surface of the first conductive layer. ### Claim 10 (depends on 1) The device according to claim 1, wherein a lower end of the metal layer is below an upper surface of the first conductive layer. ### Claim 11 (depends on 1) The device according to claim 1, further comprising: a semiconductor substrate arranged below the first conductive layer. ### Claim 12 (depends on 1) The device according to claim 1, wherein the second conductive layers include a first set of second conductive layers and a second set of second conductive layers arranged above the first set, the semiconductor memory device further comprises a second insulating layer extending in the first direction and the second direction above the first set and separating the second set of second conductive layers in the third direction, and a lower end of the second insulating layer is above the first set. ### Claim 13 (depends on 1) The device according to claim 1, wherein the device is a NAND flash memory. ### Claim 14 A semiconductor memory device, comprising: a first conductive layer; a plurality of second conductive layers arranged at intervals in a first direction above the first conductive layer; a semiconductor layer extending in the first direction in the second conductive layers so as to be in contact with the first conductive layer; a charge storage layer between the semiconductor layer and the second conductive layers; an insulating layer extending in the first direction and a second direction intersecting the first direction in the second conductive layers, and separating each of the second conductive layers in a third direction intersecting the first direction and the second direction; and a metal layer extending in the first direction and the second direction in the insulating layer, wherein the insulating layer includes a first portion between the metal layer and the first conductive layer, and a second portion between the metal layer and the second conductive layers. ### Claim 15 (depends on 14) The device according to claim 14, wherein the metal layer is insulated from the first conductive layer by the insulating layer. ### Claim 16 (depends on 14) The device according to claim 14, wherein a lower end of the metal layer is below an upper surface of the first conductive layer, and an upper end of the metal layer is above the second conductive layers. ### Claim 17 A semiconductor memory device, comprising: a first conductive layer; a plurality of second conductive layers arranged at intervals in a first direction above the first conductive layer; a first semiconductor layer extending in the first direction in the second conductive layers so as to be in contact with the first conductive layer; a first charge storage layer between the first semiconductor layer and the second conductive layers; a plurality of third conductive layers arranged at intervals in the first direction above the first conductive layer, the second conductive layers and the third conductive layers being arranged at intervals in a second direction intersecting the first direction, a second semiconductor layer extending in the first direction in the third conductive layers so as to be in contact with the first conductive layer; a second charge storage layer between the second semiconductor layer and the third conductive layers; a metal layer extending in the first direction and a third direction intersecting the first direction and the second direction, between the second conductive layers and the third conductive layers; an insulating layer including a first portion between the metal layer and the first conductive layer, a second portion between the metal layer and the second conductive layers, and a third portion between the metal layer and the third conductive layers. ### Claim 18 (depends on 17) The device according to claim 17, wherein the metal layer is insulated from the first conductive layer by the insulating layer. ### Claim 19 (depends on 17) The device according to claim 17, wherein a lower end of the metal layer is below an upper surface of the first conductive layer, and an upper end of the metal layer is above the second conductive layers and the third conductive layers.