# US 2021/0082932 A1 · Embedded memory with improved fill-in window

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- Number: US 2021/0082932 A1
- Document ID: US20210082932A1
- Status: Published application
- Kind: A1
- Application number: 17/104,686
- Filed: 2020-11-25
- Published: 2021-03-18
- Earliest claimed: 2018-06-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Meng-Han Lin; Te-Hsin Chiu; Wei Cheng Wu
- Web page: https://patentgrep.com/patent/US20210082932A1

## CPC

- H10B 41/44: with a control gate layer also being used as part of the peripheral transistor
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/68: Floating-gate IGFETs
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10P 50/264: {by chemical means}
- H10P 50/283: {by chemical means}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 52/403: {of conductive or resistive materials}
- H10P 76/2043: {using an anti-reflective coating}
- H10P 95/062: {involving a dielectric removal step}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/081: {by forming openings in the dielectric parts}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.

## Claims

### Claim 1

An integrated circuit (IC) comprising:
a memory region and a logic region integrated in a substrate;
a memory cell structure disposed on the memory region and comprising a pair of control gate electrodes respectively disposed over the substrate and a pair of select gate electrodes disposed on opposite sides of the pair of control gate electrodes;
a logic device disposed on the logic region, wherein the logic device comprises a logic gate electrode separated from the substrate by a logic gate dielectric;
a sidewall spacer disposed along a sidewall surface of the logic gate electrode; and
a contact etch stop layer (CESL) disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.

### Claim 2 (depends on 1)

The IC according to claim 1, wherein the pair of control gate electrodes and the pair of select gate electrodes comprise polysilicon.

### Claim 3 (depends on 1)

The IC according to claim 1, wherein the logic gate electrode comprises polysilicon.

### Claim 4 (depends on 1)

The IC according to claim 1, further comprises:
an inter-layer dielectric layer disposed on the contact etch stop layer (CESL) between and overlying the memory cell structure within the memory region and between the logic device within the logic region.

### Claim 5 (depends on 1)

The IC according to claim 1, wherein the logic gate dielectric comprises a high κ dielectric layer, wherein the logic gate electrode is a metal gate electrode.

### Claim 6 (depends on 1)

The IC according to claim 1, wherein the memory cell structure comprises:
first and second individual source/drain regions in the substrate on opposite sides of the pair of select gate electrodes;
a common source/drain region disposed in the substrate between the pair of control gate electrodes, wherein the common source/drain region is separated from the first individual source/drain region by a first channel region, and wherein the common source/drain region is separated from the second individual source/drain region by a second channel region; and
a pair of floating gate electrodes respectively on the first and second channel regions and separated from the pair of control gate electrodes by a control gate dielectric layer.

### Claim 7 (depends on 6)

The IC according to claim 6, further comprises:
a lower inter-layer dielectric layer disposed on the contact etch stop layer (CESL) surrounding the memory cell structure within the memory region and the logic device within the logic region, wherein the lower inter-layer dielectric layer has a planar top surface even with top surfaces of the pair of control gate electrodes and the logic gate electrode;
an upper inter-layer dielectric layer overlying the lower inter-layer dielectric layer; and
a contact disposed through the upper inter-layer dielectric layer and the lower inter-layer dielectric layer reaching the first and second individual source/drain regions.

### Claim 8

An integrated circuit (IC), comprising:
a substrate including a memory region and a logic region;
a memory cell structure disposed on the memory region and comprising a select gate electrode;
a logic device disposed on the logic region and comprising a logic gate electrode separated from the substrate by a logic gate dielectric;
a sidewall spacer along a sidewall surface of the logic gate electrode;
a lower inter-layer dielectric layer surrounding the memory cell structure; and
a contact etch stop layer (CESL) disposed along an outline of the memory cell structure and is in direct contact with a sidewall surface of the select gate electrode.

### Claim 9 (depends on 8)

The IC according to claim 8, wherein the CESL has an upper surface coplanar with that of the select gate electrode.

### Claim 10 (depends on 8)

The IC according to claim 8, wherein the memory cell structure comprises:
a floating gate electrode disposed alongside the select gate electrode; and
a control gate electrode disposed over the floating gate electrode.

### Claim 11 (depends on 10)

The IC according to claim 10, further comprises:
source/drain regions on opposite sides of the select gate electrode and the control gate electrode within the memory region and on opposite sides of the logic gate electrode within the logic region.

### Claim 12 (depends on 11)

The IC according to claim 11, further comprising:
an upper inter-layer dielectric layer disposed over the lower inter-layer dielectric layer; and
a contact through the upper inter-layer dielectric layer and the lower inter-layer dielectric layer reaching the source/drain regions within the memory region and the logic region.

### Claim 13 (depends on 10)

The IC according to claim 10, wherein the memory cell structure further comprises an erase gate electrode disposed over the substrate on one side of the control gate electrode opposite to the select gate electrode.

### Claim 14 (depends on 8)

The IC according to claim 8, wherein the logic gate electrode comprises metal.

### Claim 15 (depends on 8)

The IC according to claim 8, wherein the CESL is in direct contact with the sidewall spacer within the logic region.

### Claim 16

An integrated circuit (IC), comprising:
a substrate including a memory region and a logic region;
a memory cell structure disposed on the memory region, wherein the memory cell structure comprises a pair of control gate electrodes respectively disposed over the substrate and a pair of select gate electrodes disposed on opposite sides of the pair of control gate electrodes;
a logic device on the logic region and comprising a logic gate electrode and a logic gate dielectric stacked on the logic region;
a sidewall spacer along a sidewall surface of the logic gate electrode;
source/drain regions on opposite sides of the pair of select gate electrodes within the memory region and on opposite sides of the sidewall spacer within the logic region; and
a contact etch stop layer (CESL) along sidewalls of the memory cell structure and the logic device.

### Claim 17 (depends on 16)

The IC according to claim 16, further comprising a lower inter-layer dielectric layer surrounding the memory cell structure and the logic device.

### Claim 18 (depends on 17)

The IC according to claim 17, further comprising:
an upper inter-layer dielectric layer over the lower inter-layer dielectric layer; and
a contact through the upper inter-layer dielectric layer and the lower inter-layer dielectric layer reaching the source/drain regions within the memory region and the logic region.

### Claim 19 (depends on 16)

The IC according to claim 16, wherein the logic gate electrode is a metal gate electrode and the pair of select gate electrodes comprises polysilicon.

### Claim 20 (depends on 16)

The IC according to claim 16, wherein the CESL is in direct contact with the select gate electrodes within the memory region, and in direct contact with the sidewall spacer within the logic region.