# US 2021/0082931 A1 · Three-dimensional memory devices having through array contacts and methods for forming the same

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- Number: US 2021/0082931 A1
- Document ID: US20210082931A1
- Status: Published application
- Kind: A1
- Application number: 17/107,929
- Filed: 2020-11-30
- Published: 2021-03-18
- Earliest claimed: 2018-08-21
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Mei Lan Guo; Yushi Hu; Ji Xia; Hongbin Zhu
- Web page: https://patentgrep.com/patent/US20210082931A1

## CPC

- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved a plurality of dielectric layers and a plurality of sacrificial layers is formed above a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed in a plurality of shallow recesses and on a sidewall of the first opening. The plurality of shallow recesses abut the sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed.

## Claims

### Claim 1

A method for forming a three-dimensional (3D) memory device, comprising:
forming a stack comprising interleaved a plurality of dielectric layers and a plurality of sacrificial layers above a substrate;
forming a channel structure extending vertically through the stack;
forming a first opening extending vertically through the stack;
forming a spacer in a plurality of shallow recesses and on a sidewall of the first opening, wherein the plurality of shallow recesses abut the sidewall of the first opening;
forming a through array contact (TAC) extending vertically through the stack by depositing a conductor layer over the spacer in the first opening; and
forming a slit extending vertically through the stack.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, prior to forming the spacer, forming the plurality of shallow recesses abutting the sidewall of the first opening.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the plurality of shallow recesses comprises removing parts of the sacrificial layers abutting the sidewall of the first opening.

### Claim 4 (depends on 1)

The method of claim 1, further comprising prior to forming the first opening, forming a dummy channel structure extending vertically through the stack.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the first opening comprises simultaneously etching the first opening through the stack and a second opening outside of the stack.

### Claim 6 (depends on 5)

The method of claim 5, wherein forming the TAC comprises depositing the conductor layer in the first opening to form the TAC and in the second opening to form a peripheral contact.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the spacer on the sidewall of the first opening comprises:
depositing a dielectric layer filling in the shallow recesses and on the sidewall and a bottom surface of the first opening; and
removing part of the dielectric layer that is deposited on the bottom surface of the first opening.

### Claim 8 (depends on 7)

The method of claim 7, wherein the removal of the part of the dielectric layer comprises isotropic etching on the sidewall and the bottom surface of the first opening.

### Claim 9 (depends on 1)

The method of claim 1, wherein forming the first opening comprises:
etching the first opening through the stack, a second opening outside of the stack, and a third opening through the stack,
wherein a lateral dimension of the third opening is smaller than lateral dimensions of the first and second openings.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the spacer on the sidewall of the first opening comprises:
depositing a dielectric layer (i) in the third opening to form a dummy channel structure and (ii) in the first opening and the second opening; and
removing parts of the dielectric layer that are deposited on a bottom surface of the first opening and on a bottom surface of the second opening.

### Claim 11

A method for forming a three-dimensional (3D) memory device, comprising:
forming a lower stack comprising interleaved a plurality of dielectric layers and a plurality of sacrificial layers above a substrate;
forming a lower channel structure extending vertically through the lower stack;
forming an upper stack comprising interleaved a plurality of dielectric layers and a plurality of sacrificial layers above the lower stack;
forming an upper channel structure extending vertically through the upper stack and connecting to the lower channel structure;
forming an opening through the lower stack and the upper stack;
forming a spacer in a plurality of shallow recesses and on a sidewall of the opening, wherein the plurality of shallow recesses abut the sidewall of the opening;
depositing a conductor layer in the opening to form a through array contact (TAC); and
forming a slit extending vertically through the stack.

### Claim 12 (depends on 11)

The method of claim 11, further comprising, prior to forming the spacer, forming the plurality of shallow recesses abutting the sidewall of the opening.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the plurality of shallow recesses comprises removing parts of the sacrificial layers abutting the sidewall of the opening.

### Claim 14 (depends on 11)

The method of claim 11, wherein forming the spacer on the sidewall of the opening comprises:
depositing a dielectric layer filling in the shallow recesses and on the sidewall and a bottom surface of the opening; and
removing part of the dielectric layer that is deposited on the bottom surface of the opening.

### Claim 15 (depends on 14)

The method of claim 14, wherein the removal of the part of the dielectric layer comprises isotropic etching on the sidewall and the bottom surface of the opening.

### Claim 16 (depends on 11)

The method of claim 11, further comprising forming a slit structure by depositing a conductor layer in the slit.

### Claim 17 (depends on 11)

The method of claim 11, wherein the dielectric layers in the lower and upper stacks comprise silicon oxide, the sacrificial layers in the lower and upper stacks comprise silicon nitride, and the first and second spacers comprise silicon oxide.

### Claim 18

A method for forming a three-dimensional (3D) memory device, comprising:
forming a stack comprising interleaved a plurality of dielectric layers and a plurality of sacrificial layers above a substrate;
forming a channel structure extending vertically through the stack;
etching a first opening through the stack, a second opening outside of the stack, and a third opening through the stack
depositing a dielectric layer (i) in the third opening to form a dummy channel structure and (ii) in the first opening and the second opening;
removing parts of the dielectric layer that are deposited on a bottom surface of the first opening and on a bottom surface of the second opening;
depositing a conductor layer (i) in the first opening to form a through array contact (TAC) and (ii) in the second opening to form a peripheral contact; and
forming a slit extending vertically through the stack.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming a slit structure by depositing a conductor layer in the slit.

### Claim 20 (depends on 18)

The method of claim 18, further comprising prior to etching the first, second, and third openings, forming a staircase structure at one side of the stack.