# US 2021/0082922 A1 · Semiconductor device and method for fabricating the same

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- Number: US 2021/0082922 A1
- Document ID: US20210082922A1
- Status: Published application
- Kind: A1
- Application number: 16/570,750
- Filed: 2019-09-13
- Published: 2021-03-18
- Earliest claimed: 2019-09-13
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Chih-Wei Huang
- Web page: https://patentgrep.com/patent/US20210082922A1

## CPC

- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10D 1/692: {Electrodes}
- H10P 70/27: {during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 1/716: {having vertical extensions}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of capacitor contacts positioned over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion; a plurality of bit line contacts positioned over the substrate and a plurality of bit lines positioned over the plurality of bit line contacts, wherein at least one of the plurality of bit line is a wavy line extending between two adjacent capacitor contacts; and a capacitor structure positioned over the head portion.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a plurality of capacitor contacts positioned over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion;
a plurality of bit line contacts positioned over the substrate and a plurality of bit lines positioned over the plurality of bit line contacts, wherein at least one of the plurality of bit line is a wavy line extending between two adjacent capacitor contacts; and
a capacitor structure positioned over the head portion.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the upper width of the head portion is larger than a bottom width of the head portion.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the upper width of the neck portion is substantially the same as a bottom width of the head portion.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the head portion has a curved sidewall.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the head portion has tapered profile.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a conductive feature comprising tungsten positioned above the substrate.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the conductive feature is positioned below the plurality of capacitor structures.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the conductive feature is positioned above the plurality of capacitor structures.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, further comprising a plurality of word lines positioned in the substrate and a doped region positioned between an adjacent pair of the plurality of word lines, wherein the conductive feature is positioned on the doped region.

### Claim 11

A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a plurality of bit line contacts over a first portion of the substrate;
forming a plurality of bit lines over the plurality of bit line contacts;
forming a capacitor contact including a neck portion over a second portion of the substrate and forming a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper portion of the neck portion; and
forming a capacitor structure over the head portion;
wherein at least one of the plurality of bit line is a wavy line extending between two adjacent capacitor contacts.

### Claim 12 (depends on 11)

The method for fabricating the semiconductor device of claim 11, wherein forming a capacitor contact comprises:
forming a contact hole is a dielectric stack having a first layer and a second layer over the first layer;
removing a portion of the second layer around the contact hole to form a transformed hole having a narrow portion in the first layer and a wide portion in the second layer; and
filling a conductive material into the transformed hole.

### Claim 13 (depends on 12)

The method for fabricating the semiconductor device of claim 12, wherein the contact hole is formed integrally with a bit line trench in the second layer.

### Claim 14 (depends on 13)

The method for fabricating the semiconductor device of claim 13, further comprising:
filling the bit line trench and a lower portion of the contact hole with a filling material.

### Claim 15 (depends on 14)

The method for fabricating the semiconductor device of claim 14, wherein removing a portion of the second layer around the contact hole is performed after filling the lower portion of the contact hole with a sacrificial material.

### Claim 16 (depends on 11)

The method for fabricating the semiconductor device of claim 11, further comprising:
forming a conductive feature comprising tungsten positioned above the substrate; and
forming a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature.

### Claim 17 (depends on 12)

The method for fabricating the semiconductor device of claim 12, further comprising: cleaning the conductive feature before forming a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature, wherein cleaning the conductive feature comprises applying a reducing agent to the top surface of the conductive feature, and the reducing agent is titanium tetrachloride, tantalum tetrachloride, or a combination thereof.

### Claim 18 (depends on 16)

The method for fabricating the semiconductor device of claim 16, further comprising forming a plurality of capacitor structures positioned above the capacitor contacts.

### Claim 19 (depends on 18)

The method for fabricating the semiconductor device of claim 18, wherein the conductive feature is positioned below the plurality of capacitor structures.

### Claim 20 (depends on 18)

The method for fabricating the semiconductor device of claim 18, wherein the conductive feature is positioned above the plurality of capacitor structures.