# US 2021/0082920 A1 · Semiconductor device

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- Number: US 2021/0082920 A1
- Document ID: US20210082920A1
- Status: Published application
- Kind: A1
- Application number: 16/961,976
- Filed: 2019-01-15
- Published: 2021-03-18
- Earliest claimed: 2018-01-25
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Yusuke NONAKA; Noritaka ISHIHARA; Tomoki HIRAMATSU; Ryunosuke HONDA; Tomoyo KAMOGAWA; Ryota HODO; Katsuaki TOCHIBAYASHI; Shunpei YAMAZAKI
- Web page: https://patentgrep.com/patent/US20210082920A1

## CPC

- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device having high operation frequency is provided. The semiconductor device includes a transistor including a first conductive layer, a first insulating layer, a second insulating layer, a first oxide, a second oxide, a third oxide, a third insulating layer, and a second conductive layer that are stacked in this order, and a fourth insulating layer. The first conductive layer and the second conductive layer include a region overlapping with the second oxide. In a channel width direction of the transistor, a level of the bottom surface of the second oxide is from more than or equal to −5 nm to less than 0 nm when a level of a region of the bottom surface of the second conductive layer which does not overlap with the second oxide is regarded as a reference.

## Claims

### Claim 1

A semiconductor device comprising a transistor, and the transistor comprising:
a first conductive layer;
a first insulating layer over the first conductive layer;
a second insulating layer over the first insulating layer;
a first oxide over the second insulating layer;
a second oxide over the first oxide;
a third oxide over the second oxide;
a third insulating layer over the third oxide;
a second conductive layer over the third insulating layer; and
a fourth insulating layer,
wherein the first conductive layer and the second conductive layer overlap with the second oxide,
wherein side surfaces of the second conductive layer, the third insulating layer, and the third oxide are substantially aligned,
wherein the fourth insulating layer is in contact with the side surfaces of the second conductive layer, the third insulating layer, and the third oxide, and
wherein in a channel width direction of the transistor, a bottom surface of the second oxide is below a region of a bottom surface of the second conductive layer,
wherein the region of the bottom surface of the second conductive layer does not overlap with the second oxide and the first oxide, and
wherein when a level of the region of the bottom surface of the second conductive layer is regarded as a reference, a level of the bottom surface of the second oxide from the reference is more than or equal to −5 nm to less than 0 nm.

### Claim at position 2

-5. (canceled)

### Claim 6 (depends on 1)

The semiconductor device according to claim 1,
wherein a side surface of the second insulating layer is substantially aligned with side surfaces of the first oxide and the second oxide, and
wherein the third oxide is in contact with a top surface of the second insulating layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1,
wherein, when a level of a bottom surface of the first insulating layer is regarded as a reference, a level of a first region of a top surface of the second insulating layer which overlaps with the second oxide is higher than a level of a second region of the top surface of the second insulating layer which does not overlap with the second oxide.

### Claim 8

A semiconductor device comprising a transistor, and the transistor comprising:
a first conductive layer;
a first insulating layer over the first conductive layer;
a second insulating layer over the first insulating layer;
a first oxide over the second insulating layer;
a second oxide over the first oxide;
a third oxide over the second oxide;
a third insulating layer over the third oxide;
a second conductive layer over the third insulating layer;
a third conductive layer and a fourth conductive layer over the second oxide;
a fifth conductive layer over the third conductive layer; and
a sixth conductive layer over the fourth conductive layer,
wherein the first conductive layer and the second conductive layer overlap with the second oxide,
wherein the fifth conductive layer is in contact with a side surface of the third conductive layer on a second conductive layer side, and in contact with a top surface of the second oxide,
wherein the sixth conductive layer is in contact with a side surface of the fourth conductive layer on the second conductive layer side, and in contact with the top surface of the second oxide,
wherein, in a channel width direction of the transistor, a bottom surface of the second oxide is below a first region of a bottom surface of the second conductive layer,
wherein the first region of the bottom surface of the second conductive layer does not overlap with the second oxide and the first oxide, and
wherein, when a level of the first region of the bottom surface of the second conductive layer is regarded as a reference, a level of the bottom surface of the second oxide from the reference is more than or equal to −5 nm to less than 0 nm.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein in a cross section in a channel length direction of the transistor, when a level of a bottom surface of the first insulating layer is regarded as a reference, a level of a second region of the bottom surface of the second conductive layer which overlaps with the second oxide is less than or equal to a level of a top surface of the third conductive layer.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8,
wherein a side surface of the second insulating layer is substantially aligned with side surfaces of the first oxide and the second oxide, and
wherein the third oxide is in contact with a top surface of the first insulating layer.

### Claim 11 (depends on 8)

The semiconductor device according to claim 8,
wherein when a level of a bottom surface of the first insulating layer is regarded as a reference, a level of a first region of a top surface of the second insulating layer which overlaps with the second oxide is higher than a level of a second region of the top surface of the second insulating layer which does not overlap with the second oxide.

### Claim 12

A semiconductor device comprising a transistor, and the transistor comprising:
a first gate electrode;
a first insulating layer over the first gate electrode;
a second insulating layer over the first insulating layer;
a first oxide semiconductor layer over the second insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer over the second oxide semiconductor layer;
a third insulating layer over the third oxide semiconductor layer; and
a second gate electrode over the third insulating layer,
wherein in a channel width direction of the transistor, a bottom surface of the second oxide semiconductor layer is below a region of a bottom surface of the second gate electrode,
wherein the region of the bottom surface of the second gate electrode does not overlap with the second oxide semiconductor layer and the first oxide semiconductor layer, and
wherein when a level of the region of the bottom surface of the second gate electrode is regarded as a reference, a level of the bottom surface of the second oxide semiconductor layer from the reference is more than or equal to −10 nm to less than 0 nm.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12,
wherein a side surface of the second insulating layer is substantially aligned with side surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer, and
wherein the third oxide semiconductor layer is in contact with a top surface of the second insulating layer.

### Claim 14 (depends on 12)

The semiconductor device according to claim 12,
wherein, when a level of a bottom surface of the first insulating layer is regarded as a reference, a level of a first region of a top surface of the second insulating layer is higher than a level of a second region of the top surface of the second insulating layer, and
wherein the first region of the top surface of the second insulating layer overlap with the second oxide semiconductor layer and the second region of the top surface of the second insulating layer does not overlap with the second oxide semiconductor layer.