# US 2021/0082918 A1 · Integrated Circuit Device With Low Threshold Voltage

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- Number: US 2021/0082918 A1
- Document ID: US20210082918A1
- Status: Published application
- Kind: A1
- Application number: 16/573,866
- Filed: 2019-09-17
- Published: 2021-03-18
- Earliest claimed: 2019-09-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chung-Liang Cheng; Ziwei Fang
- Web page: https://patentgrep.com/patent/US20210082918A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 14/3216: {Nitrides}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6938: {the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides}
- H10P 14/69393: {the material containing tantalum, e.g. Ta2O5}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
providing a substrate having a first region and a second region;
forming an n-type work function layer over the substrate in the first region but not in the second region; and
forming a p-type work function layer, wherein the p-type work function layer includes a metal oxide, wherein the p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region, and wherein the p-type work function layer directly contacts the substrate in the second region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the n-type work function layer includes:
forming a first layer containing tantalum and nitrogen over a gate dielectric layer;
etching back the first layer; and
depositing the n-type work function layer over the etched back first layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming the n-type work function layer includes:
forming the n-type work function layer over the substrate in both the first region and the second region; and
patterning and removing the n-type work function layer in the second region but not in the first region.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming the p-type work function layer includes:
forming a metal layer over the n-type work function layer; and
converting the metal layer into a metal oxide layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the forming the metal layer includes:
forming a ruthenium layer with triruthenium dodecacarbonyl (Ru3(CO)12) and hydrogen (H2) as precursors by an in-situ ALD deposition at a temperature of about 100° C. to about 200° C. and at a total pressure of about 5 torr to about 15 torr; and
tuning a thickness of the ruthenium layer by adjusting a process time of the in-situ ALD deposition.

### Claim 6 (depends on 4)

The method of claim 4, wherein the converting the metal layer includes conducting an oxygen plasma treatment of the metal layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the oxygen plasma treatment is conducted at a temperature between about 160° C. to about 250° C. and with an oxygen flow rate of about 2,000 standard cubic centimeters per minute (sccm) to about 6,000 sccm.

### Claim 8 (depends on 6)

The method of claim 6, further comprising forming a capping layer over the p-type work function layer, and wherein the conducting the oxygen plasma treatment includes conducting the oxygen plasma treatment through the capping layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the forming the metal layer includes pre-cleaning a surface of the capping layer, wherein the pre-cleaning includes partially etching-back the capping layer with a chemical selected from tantalum pentachloride (TaCl5) and tungsten pentachloride (WCl5) at a processing temperature of about 300° C. to about 500° C., and at a total pressure of about 5 torr to about 15 torr.

### Claim 10 (depends on 8)

The method of claim 8, wherein the forming the capping layer includes:
depositing a tantalum nitride (TaN) layer by an Atomic Layer Deposition (ALD) method with pentakis(dimethylamino) tantalum (PDMAT) and ammonia (NH3) at a temperature between about 225° C. and about 275° C.; and
tuning a thickness of the capping layer by adjusting a cycle number of the ALD method.

### Claim 11 (depends on 1)

The method of claim 1, wherein the providing the substrate includes providing a semiconductor structure having a plurality of semiconductor layers that are vertically stacked over one another, wherein the forming the n-type work function layer includes forming the n-type work function layer over a first semiconductor layer of the plurality of semiconductor layers, and wherein the p-type work function layer in the second region directly contacts the first semiconductor layer.

### Claim 12

A method to manufacture an integrated circuit (IC) device, comprising:
forming a first opening in a first gate structure and a second opening in a second gate structure, wherein the first gate structure is disposed over a first fin structure and the second gate structure is disposed over a second fin structure;
forming a gate dielectric layer in the first and the second openings;
forming an n-type work function layer in the first and the second openings;
removing the n-type work function layer in the second opening, but not in the first opening;
forming a p-type work function layer in the first and the second openings, wherein the p-type work function layer includes a metal oxide; and
forming a metal fill layer over the p-type work function layer in the first and the second openings.

### Claim 13 (depends on 12)

The method of claim 12, wherein the forming the p-type work function layer includes forming the p-type work function layer that includes ruthenium oxide.

### Claim 14 (depends on 12)

The method of claim 12, wherein the forming the p-type work function layer includes:
forming a metal layer;
forming a capping layer over the metal layer; and
treating the metal layer through the capping layer with an oxygen plasma.

### Claim 15 (depends on 12)

The method of claim 12, wherein the forming the gate dielectric layer includes:
forming a capping layer over the gate dielectric layer;
performing an annealing process; and
removing the capping layer.

### Claim 16

A device comprising:
a substrate including a semiconductor material;
a first gate structure in an n-type region of the substrate; and
a second gate structure in a p-type region of the substrate,
wherein the first gate structure includes a p-type work function layer deposited over an n-type work function layer,
wherein the second gate structure includes the p-type work function layer deposited over and directly contacting the substrate, and
wherein the p-type work function layer includes ruthenium oxide (RuO2).

### Claim 17 (depends on 16)

The device of claim 16, wherein the second gate structure includes a capping layer over the p-type work function layer, and wherein the capping layer includes tantalum and nitrogen.

### Claim 18 (depends on 16)

The device of claim 16, wherein the first gate structure includes a plurality of semiconductor layers, and wherein the n-type work function layer is disposed over the plurality of semiconductor layers.

### Claim 19 (depends on 16)

The device of claim 16, wherein the p-type work function layer has a thickness between about 10 Å and about 15 Å.

### Claim 20 (depends on 16)

The device of claim 16, wherein the p-type work function layer includes both ruthenium oxide and unoxidized ruthenium.