# US 2021/0082915 A1 · Multi-threshold voltage non-planar complementary metal-oxide-semiconductor devices

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- Number: US 2021/0082915 A1
- Document ID: US20210082915A1
- Status: Published application
- Kind: A1
- Application number: 16/573,348
- Filed: 2019-09-17
- Published: 2021-03-18
- Earliest claimed: 2019-09-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruqiang Bao; Koji Watanabe
- Web page: https://patentgrep.com/patent/US20210082915A1

## CPC

- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/837: {comprising vertical IGFETs}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.

## Claims

### Claim 1

A device, comprising:
an interfacial layer on a semiconductor device channel;
a dipole layer on the interfacial layer;
a gate dielectric layer on the dipole layer;
a first work function layer associated with a first field effect transistor device; and
a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.

### Claim 2 (depends on 1)

The pair of field effect transistor devices of claim 1, wherein the dipole layer is aluminum oxide (AlO).

### Claim 3 (depends on 1)

The pair of field effect transistor devices of claim 1, wherein the second work function layer is also on the first work function layer on the first field effect transistor device.

### Claim 4 (depends on 1)

The pair of field effect transistor devices of claim 1, wherein the first field effect transistor device and the second field effect transistor device are both nanosheet type transistor devices.

### Claim 5 (depends on 1)

The pair of field effect transistor devices of claim 1, wherein the first field effect transistor device and the second field effect transistor device are both vertical transport field effect transistor devices.

### Claim 6

A plurality of field effect transistor devices each having a gate structure, comprising:
an interfacial layer on each semiconductor device channel of the plurality of field effect transistor devices, wherein a first set of the plurality of field effect transistor devices are n-type field effect transistor devices and a second set of field effect transistor devices are p-type field effect transistor devices;
a dipole layer on the interfacial layer on each of a subset of the plurality of field effect transistor devices, wherein at least one of the dipole layers is on at least one of the n-type field effect transistor devices and at least another one of the dipole layers is on at least one of the p-type field effect transistor devices;
a gate dielectric layer on each of the interfacial layers;
a first work function layer on the gate dielectric layer on the first set of the plurality of field effect transistor devices; and
a second work function layer on the gate dielectric layer on the second set of the plurality of field effect transistor devices, wherein the first work function layer is a work function material (WFM) different from the second work function layer.

### Claim 7 (depends on 6)

The plurality of field effect transistor devices of claim 6, wherein the plurality of field effect transistor devices includes at least four field effect transistor devices.

### Claim 8 (depends on 7)

The plurality of field effect transistor devices of claim 7, wherein the first set of the plurality of field effect transistor devices includes at least two field effect transistor devices, and the second set of the plurality of field effect transistor devices includes at least two field effect transistor devices.

### Claim 9 (depends on 8)

The plurality of field effect transistor devices of claim 8, wherein the dipole layers are on at least two of the first set of the plurality of field effect transistor devices, and the dipole layers are on at least two of the second set of the plurality of field effect transistor devices.

### Claim 10 (depends on 9)

The plurality of field effect transistor devices of claim 9, wherein one of the first set of the plurality of field effect transistor devices has a threshold voltage higher than another of the first set of the plurality of field effect transistor devices.

### Claim 11 (depends on 9)

The plurality of field effect transistor devices of claim 9, wherein one of the second set of the plurality of field effect transistor devices has a threshold voltage lower than another of the second set of the plurality of field effect transistor devices.

### Claim 12

A method of fabricating a plurality of field effect transistor devices each having a gate structure, comprising:
forming a plurality of semiconductor device channels on a substrate;
forming an interfacial layer on each of the plurality of semiconductor device channels;
forming a gate dielectric layer on the interfacial layers;
forming a conversion layer segment on the gate dielectric layer on a subset of the plurality of semiconductor device channels;
forming a capping layer on each of the plurality of semiconductor device channels;
forming a cover layer on the plurality of semiconductor device channels; and
heat treating the conversion layer segments and plurality of semiconductor device channels to form a dipole layer between the interfacial layer and gate dielectric layer on the subset of the plurality of semiconductor device channels.

### Claim 13 (depends on 12)

The method of claim 12, wherein the conversion layer segments is an aluminum-containing material selected from the group consisting of aluminum oxide (AlO), titanium-aluminum alloys (TiAl), aluminum metal (Al), and combinations thereof.

### Claim 14 (depends on 12)

The method of claim 12, wherein each of the plurality of semiconductor device channels are formed by a stack of nanosheet layers.

### Claim 15 (depends on 12)

The method of claim 12, wherein the plurality of semiconductor device channels are formed by vertical fins.

### Claim 16 (depends on 15)

The method of claim 15, further comprising removing the cover layer and forming a first work function layer on the capping layer on each of the plurality of semiconductor device channels.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming a masking block on a first set of the plurality of vertical fins, and removing the first work function layer and the capping layer from an exposed second set of vertical fins.

### Claim 18 (depends on 15)

The method of claim 15, further comprising reducing the height of the cover layer to expose an upper portion of the capping layer on each of the plurality of semiconductor device channels.

### Claim 19 (depends on 18)

The method of claim 18, further comprising removing the exposed portions of the capping layer.

### Claim 20 (depends on 19)

The method of claim 19, further comprising replacing a portion of the reduced height cover layer with a first work function layer.