# US 2021/0082912 A1 · Semiconductor device

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- Number: US 2021/0082912 A1
- Document ID: US20210082912A1
- Status: Published application
- Kind: A1
- Application number: 17/107,672
- Filed: 2020-11-30
- Published: 2021-03-18
- Earliest claimed: 2018-12-19
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Tohru SHIRAKAWA
- Web page: https://patentgrep.com/patent/US20210082912A1

## CPC

- H10D 84/817: {Combinations of field-effect devices and resistors only}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D 1/47: Resistors having no potential barriers
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 89/10: Integrated device layouts
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10W 72/926: {Multiple bond pads having different sizes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An active region has first and second cell regions respectively disposed in a main IGBT and a sensing IGBT. The second cell region has a detecting region in which the sensing IGBT is disposed and an extracting region that surrounds a periphery of the detecting region. A resistance region containing polysilicon and connected to the sensing IGBT is provided on the semiconductor substrate, in the extracting region. The resistance region connected to the sensing IGBT has a first portion connected to the gate electrodes of the sensing IGBT and a second portion connecting the first portion to the gate runner, and configures a built-in resistance of the second portion having a resistance value in a range from 10Ω to 5000Ω. As a result, a trade-off relationship between enhancing ESD tolerance of a current sensing region that includes the sensing IGBT and reducing transient sensing voltage may be improved.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
an active region provided on the semiconductor substrate; and
a termination region provided in the semiconductor substrate, surrounding a periphery of the active region, wherein
the active region includes:
a first cell region in which a first insulated-gate-type bipolar transistor is disposed, and
a second cell region disposed adjacent to the first cell region, wherein
the second cell region includes:
a first region in which a second insulated-gate-type bipolar transistor is disposed, the second insulated-gate-type bipolar transistor having an arithmetic area smaller than that of the first insulated-gate-type bipolar transistor, and
a second region separating the first cell region from the first region, wherein
the second region includes:
a first gate electrode layer provided on the semiconductor substrate via an oxide film, and
an emitter electrode of the second insulated-gate-type bipolar transistor, provided on the first gate electrode layer via an interlayer insulating film, wherein
the termination region comprises a gate runner provided on the semiconductor substrate via the oxide film, the gate runner surrounding a periphery of the active region, and being electrically connected to a plurality of first gate electrodes of the first insulated-gate-type bipolar transistor, wherein
the first gate electrode layer has:
a first gate electrode layer portion electrically connected to a plurality of second gate electrodes of the second insulated-gate-type bipolar transistor, and
a second gate electrode layer portion in the second region, having a planar shape in a plane parallel to a surface of the semiconductor substrate and extending from the first gate electrode layer portion to the gate runner, the second gate electrode layer portion electrically connecting the first gate electrode layer portion and the gate runner, and wherein
the second gate electrode layer portion has a resistance value in a range from 10Ω to 5000Ω.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the second gate electrode layer portion, in the plane parallel to the surface of the semiconductor substrate, linearly extends from the first gate electrode layer portion to the gate runner, to connect the first gate electrode layer portion and the gate runner.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
the second gate electrode layer portion, in the plane parallel to the surface of the semiconductor substrate, meanders and extends from the first gate electrode layer portion to the gate runner, to connect the first gate electrode layer portion and the gate runner.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein
the second gate electrode layer portion, in the plane parallel to the surface of the semiconductor substrate, extends in an L-shape along an outer periphery of the second region, from the first gate electrode layer portion to the gate runner, to connect the first gate electrode layer portion and the gate runner.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein
the second gate electrode layer portion includes two second gate electrode layer portions between the first gate electrode layer portion and the gate runner, connected in parallel.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein
the gate runner has an extended portion extending in the active region, along an outer periphery of the second region and surrounding a periphery of the first region, and wherein
the second gate electrode layer portion, in the plane parallel to the surface of the semiconductor substrate, extends from the first gate electrode layer portion to the extended portion of the gate runner, to connect the first gate electrode layer portion and the extended portion of the gate runner.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, further comprising:
in the active region, a third region that is a portion excluding the first cell region and the second cell region, and that is disposed adjacent to the termination region;
in the third region, a second gate electrode layer provided on the semiconductor substrate via the oxide film; and
a gate pad provided on the second gate electrode layer via the interlayer insulating film, wherein
the second gate electrode layer has:
a third gate electrode layer portion facing the gate pad, across the interlayer insulating film in a direction orthogonal to the surface of the semiconductor substrate, and
a fourth gate electrode layer portion in the third region, having a planar shape in a plane parallel to the surface of the semiconductor substrate, and extending from the third gate electrode layer portion to the gate runner, the fourth gate electrode layer portion electrically connecting the third gate electrode layer portion and the gate runner.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein
the first insulated-gate-type bipolar transistor has a trench gate structure having the first gate electrodes extending in a depth direction of the semiconductor substrate.