# US 2021/0082909 A1 · Semiconductor apparatus and system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082909 A1 - Document ID: US20210082909A1 - Status: Published application - Kind: A1 - Application number: 17/108,824 - Filed: 2020-12-01 - Published: 2021-03-18 - Earliest claimed: 2017-06-08 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Joong-Ho KIM; Hyun Woo KWACK; Ki Jong LEE; Doo Bock LEE - Web page: https://patentgrep.com/patent/US20210082909A1 ## CPC - H10D 89/931: {characterised by the dispositions of the protective arrangements} - H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits} - H10D 89/911: {using passive elements as protective elements} - H10D 89/921: {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses} - H10W 90/00: Package configurations - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit. ## Claims ### Claim 1 A semiconductor device comprising: a first receiving circuit configured to be electrically coupled to an external device via a first external connection terminal; a second receiving circuit configured to be electrically coupled to the external device via a second external connection terminal; a first electrostatic discharge protection circuit configured to be connected between the first receiving circuit and the first external connection terminal; a second electrostatic discharge protection circuit configured to be connected between the second receiving circuit and the second external connection terminal; and a load compensation circuit configured to compensate difference of loads between the external device and the external connection terminals; wherein the load compensation circuit is connected to at least one of the first electrostatic discharge protection circuit and the second electrostatic discharge protection circuit and the load compensation circuit and the one of electrostatic discharge circuit are electrically parallel to each other. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein a length between the first external connection terminal and the external device is different from a length between the second external connection terminal and the external device. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the load compensation circuit includes at least one of a capacitor and resistor. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the load compensation circuit has one end to which the external connection terminal is coupled and another end to which the external connection terminal is not coupled. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the electrostatic discharge circuit includes at least one of a capacitor and a resistor. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the external connection terminals are electrically coupled to another semiconductor device. ### Claim 7 A semiconductor system comprising: a control device; a first semiconductor device configured to be electrically coupled to the control device via a line; a second semiconductor device configured to be electrically coupled to the control device via the line; wherein at least one of the semiconductor devices include a electrostatic discharge protection circuit and a load compensation circuit and the electrostatic discharge protection circuit and the load compensation circuit are electrically parallel to each other, and the load compensation circuit compensates by adding capacitive loading depending on loads between the control device and the semiconductor devices. ### Claim 8 (depends on 7) The semiconductor system according to claim 7, wherein the electrostatic discharge protection circuit includes at least one of a capacitor and a resistor. ### Claim 9 (depends on 7) The semiconductor system according to claim 7, wherein the load compensation circuit includes at least one of a capacitor and a resistor. ### Claim 10 (depends on 7) The semiconductor system according to claim 7, wherein the first semiconductor device and the second semiconductor device include an external connection terminal and a receiving circuit respectively, ### Claim 11 (depends on 10) The semiconductor system according to claim 10, wherein the electrostatic discharge protection circuit and the load compensation circuit are connected between the external connection terminal and the receiving circuit. ### Claim 12 (depends on 11, 12) The semiconductor system according to claim 11, wherein the first semiconductor device and the second semiconductor device receives same control signals via the external connection terminal at different times. 13, The semiconductor system according to claim 12, wherein a time difference reaching the control signal at the external connection terminals is greater than at the receiving circuits. ### Claim 14 (depends on 7) The semiconductor system according to claim 7, wherein the first semiconductor device and the second semiconductor device are packaged semiconductor independently. ### Claim 15 (depends on 7) The semiconductor system according to claim 7, wherein the semiconductor system includes a package substrate and a molding structure which molds the first semiconductor device and the second semiconductor device. ### Claim 16 (depends on 7) The semiconductor system according to claim 7, wherein the semiconductor system includes a third semiconductor device, the third semiconductor device is electrically coupled to the control device via another line.