# US 2021/0082908 A1 · Semiconductor storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082908 A1 - Document ID: US20210082908A1 - Status: Published application - Kind: A1 - Application number: 16/937,825 - Filed: 2020-07-24 - Published: 2021-03-18 - Earliest claimed: 2019-09-12 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Takehiro NAKAI - Web page: https://patentgrep.com/patent/US20210082908A1 ## CPC - H10D 89/931: {characterised by the dispositions of the protective arrangements} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - H10D 89/911: {using passive elements as protective elements} - H10W 10/031: {of isolation regions comprising PN junctions} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W 10/30: Isolation regions comprising PN junctions - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor storage device includes a circuit region formed on a semiconductor substrate, and a guard ring region spaced from one side of the circuit region by a predetermined distance. The guard ring region extends in a first direction, the first direction being a direction in which the one side of the circuit region extends, includes a guard ring line, an element isolation region, a first defect trapping layer, a second defect trapping layer. The first defect trapping layer extends from a boundary location between the circuit region and the element isolation region to a location spaced from a boundary location between the element isolation region and the guard ring line by an offset distance toward the element isolation region in the second direction. ## Claims ### Claim 1 A semiconductor storage device, comprising: a circuit region formed on a semiconductor substrate; and a guard ring region spaced from one side of the circuit region by a predetermined distance, wherein the guard ring region extends in a first direction, the first direction being a direction in which the one side of the circuit region extends, includes: a guard ring line, wherein the guard ring line includes a plurality of guard ring patterns over a surface of the semiconductor substrate, each of the plurality of guard ring patterns include a first line segment extending in the first direction, a second line segment extending from a first end of the first line segment in a second direction orthogonal to the first direction, and a third line segment extending from a second end of the first line segment in the second direction, wherein in a first one and a second one of the plurality of guard ring patterns adjacent to each other, the second line segment of the first guard ring pattern is connected to the third line segment of the second guard ring pattern by a fourth line segment extending in the second direction; an element isolation region, formed between the circuit region and the guard ring line, that extends into the semiconductor substrate to a first depth; a first defect trapping layer, which is a highly distorted layer, formed below the element isolation region; and a second defect trapping layer, which is a highly distorted layer, formed along a boundary between the element isolation region and the circuit region, the second defect trapping layer extending into the semiconductor substrate to a second depth equal to the first depth, wherein the first defect trapping layer extends from a boundary location between the circuit region and the element isolation region to a location spaced from a boundary location between the element isolation region and the guard ring line by an offset distance toward the element isolation region in the second direction. ### Claim 2 (depends on 1) The semiconductor storage device according to claim 1, wherein the fourth line segment connects one end of the second line segment of the first guard ring pattern, which is not connected to the first line segment of the first guard ring pattern, to one end of the third line segment of the second guard ring pattern, which is not connected to the first line segment of the second guard ring pattern. ### Claim 3 (depends on 1) The semiconductor storage device according to claim 1, wherein the guard ring line has a meander-shaped planar shape. ### Claim 4 (depends on 1) The semiconductor storage device according to claim 1, wherein the first line segment extends in the first direction from a first connection part at an intersection of the first line segment and the second line segment, and the second line segment extends in the first and second directions from the first connection part, the first line segment extends in the first direction from a second connection part at an intersection of the first line segment and the third line segment, and the third line segment extends in the second direction from the second connection part, the fourth line segment extends in the first direction from a third connection part at an intersection of the fourth line segment and the second line segment, and the second line segment extends in the first and second directions from the third connection part, and the fourth line segment extends in the first direction from a fourth connection part at an intersection of the fourth line segment and the third line segment, and the third line segment extends in the second direction from the fourth connection part. ### Claim 5 (depends on 1) The semiconductor storage device according to claim 1, wherein the fourth line segment connects one end of the second line segment of the first guard ring pattern, which is connected to the first line segment of the first guard ring pattern, to one end of the third line segment of the second guard ring pattern, which is connected to the first line segment of the second guard ring pattern. ### Claim 6 (depends on 1) The semiconductor storage device according to claim 1, wherein the guard ring line has a comb-shaped planar shape. ### Claim 7 (depends on 1) The semiconductor storage device according to claim 1, wherein the offset distance is equal to or greater than a width of the first line segment extending in the second direction. ### Claim 8 (depends on 1) The semiconductor storage device according to claim 1, wherein each of the first defect trapping layer and the second defect trapping layer contains impurities implanted in a high concentration. ### Claim 9 (depends on 8) The semiconductor storage device according to claim 8, wherein the impurities include at least one of carbon or oxygen. ### Claim 10 (depends on 8) The semiconductor storage device according to claim 8, wherein the impurities include boron. ### Claim 11 (depends on 10) The semiconductor storage device according to claim 10, wherein the second defect trapping layer is formed along the boundary location between the element isolation region and the circuit region, and the second defect trapping layer is formed at least near a third connection part at an intersection of the fourth line segment and the second line segment and a fourth connection part at an intersection of the fourth line segment and the third line segment. ### Claim 12 (depends on 1) The semiconductor storage device according to claim 1, wherein each of the first defect trapping layer and the second defect trapping layer includes a first material different from a second material of the semiconductor substrate. ### Claim 13 (depends on 12) The semiconductor storage device according to claim 12, wherein the first material includes at least one of polycrystalline silicon, silicon oxide, or silicon nitride.