# US 2021/0082906 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082906 A1 - Document ID: US20210082906A1 - Status: Published application - Kind: A1 - Application number: 16/575,091 - Filed: 2019-09-18 - Published: 2021-03-18 - Earliest claimed: 2019-09-18 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Po-Lin PENG; Li-Wei CHU; Ming-Fu TSAI; Jam-Wem LEE; Yu-Ti SU - Web page: https://patentgrep.com/patent/US20210082906A1 ## CPC - H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices} - H10D 8/80: PNPN diodes, e.g. Shockley diodes or break-over diodes - H10D 89/10: Integrated device layouts - H10D 89/611: {using diodes as protective elements} - H10D 8/411: {PN diodes having planar bodies} - H10D 18/80: Bidirectional devices, e.g. triacs - H10D 62/133: {Emitter regions of BJTs} - H10D 62/137: {Collector regions of BJTs} - H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs} - H10D 84/613: {Combinations of vertical BJTs and one or more of diodes, resistors or capacitors} - H10D 84/615: {Combinations of vertical BJTs and one or more of resistors or capacitors} - H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] - H10D 89/911: {using passive elements as protective elements} - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 42/80: protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal. ## Claims ### Claim 1 A semiconductor device, comprising: a first diode, wherein a first terminal of the first diode is coupled to a first voltage terminal that is configured to receive a first supply voltage; a second diode, wherein a first terminal of the second diode, an input/output (I/O) pad, and a second terminal of the first diode are coupled to each other, and a second terminal of the second diode is coupled to a second voltage terminal that is configured to receive a second supply voltage; a clamp circuit coupled between the first voltage terminal and the second voltage terminal, wherein the second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal; and a third diode, wherein a first terminal and a second terminal of the third diode are coupled to the first voltage terminal; wherein the second diode and the third diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first semiconductor structure in the second diode and the third diode is configured to operate as an equivalent silicon controlled rectifier (SCR) circuit. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first semiconductor structure in the second diode and the third diode comprises: a substrate; a first well of a first type disposed on the substrate; a first doped region of the first type disposed in the first well and configured as the second terminal of the second diode; a second doped region of a second type disposed in the first well and configured as the first terminal of the second diode; a second well of the second type disposed on the substrate and adjacent to the first well; a third doped region of the first type disposed in the second well and configured as the first terminal of the third diode; and a fourth doped region of the second type disposed in the second well and configured as the second terminal of the third diode; wherein the second doped region, the first well, the substrate, the second well, and the third doped region are configured to operate as an equivalent silicon controlled rectifier (SCR) circuit. ### Claim 4 (depends on 1) The semiconductor device of claim 1, further comprising: at least one of a fourth diode coupled to the first diode in parallel between the I/O pad and the first voltage terminal, a fifth diode coupled to the second diode in parallel between the I/O pad and the second voltage terminal, or a sixth diode coupled to the third diode in parallel. ### Claim 5 (depends on 1) The semiconductor device of claim 1, further comprising: a fourth diode, wherein a first terminal and a second terminal of the fourth diode are coupled to the second voltage terminal, wherein the fourth diode and the third diode include a second semiconductor structure configured to direct a third part of the ESD current, from the second voltage terminal to the first voltage terminal, or from the first voltage terminal to the second voltage terminal. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the third diode and the fourth diode are configured to operate as an equivalent silicon controlled rectifier (SCR) circuit. ### Claim 7 (depends on 5) The semiconductor device of claim 5, wherein the first semiconductor structure comprises: a substrate; a first well of a first type disposed on the substrate; a first doped region of the first type disposed in the first well and configured as the second terminal of the second diode; a second doped region of a second type disposed in the first well and configured as the first terminal of the second diode; a second well of the second type disposed on the substrate and adjacent to the first well; a third doped region of the first type disposed in the second well and configured as the first terminal of the third diode; and a fourth doped region of the second type disposed in the second well and configured as the second terminal of the third diode; wherein the second doped region, the first well, the substrate, the second well, and the third doped region are configured to operate as an equivalent silicon controlled rectifier (SCR) circuit; wherein the second semiconductor structure comprises: the substrate; the third doped region; the fourth doped region; a third well of a first type disposed on the substrate and adjacent to the second well; a fifth doped region of the first type disposed in the third well and configured as the first terminal of the fourth diode; and a sixth doped region of the second type disposed in the third well and configured as the second terminal of the fourth diode; wherein the third doped region, the second well, the substrate, the third well, and the sixth doped region are configured to operate as a second equivalent silicon controlled rectifier circuit. ### Claim 8 A semiconductor device, comprising: a substrate; a first well of a first type, disposed on the substrate; a first doped region of the first type, disposed in the first well, wherein the first doped region is configured as a first terminal of a first diode and is coupled to a first voltage terminal configured to receive a first supply voltage; a second doped region of a second type disposed in the first well, wherein the second doped region is configured as a second terminal of the first diode and is coupled to an input/output (I/O) pad; a second well of the second type disposed on the substrate and adjacent to the first well; a third doped region of the first type, disposed in the second well, wherein the third doped region is configured as a first terminal of a second diode and is coupled to a second voltage terminal configured to receive a second supply voltage; and a fourth doped region of the second type disposed in the second well, wherein the fourth doped region is configured as a second terminal of the second diode and is coupled to the second voltage terminal; wherein the first diode, the first voltage terminal, and a clamp circuit coupled between the first voltage terminal and the second voltage terminal are configured as a first electrostatic discharge (ESD) path between the I/O pad and the second voltage terminal, and wherein the second doped region, the first well, the substrate, the second well, and the third doped region are configured as a second ESD path between the I/O pad and the second voltage terminal. ### Claim 9 (depends on 8) The semiconductor device of claim 8, further comprising: a third well of the second type, disposed on the substrate and adjacent to the first well; a fifth doped region of the first type, disposed in the third well, wherein the fifth doped region is configured as a first terminal of a third diode and is coupled to the I/O pad; and at least one sixth doped region of the second type, disposed in the third well, wherein the at least one sixth doped region is configured as a second terminal of the third diode and is coupled to the second voltage terminal. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the first to third wells, the first to fifth doped regions, and the at least one sixth doped regions are configured in a cell of a layout of the semiconductor device, and the semiconductor device further comprises: a plurality of the cells arranged in an array. ### Claim 11 (depends on 9) The semiconductor device of claim 9, wherein the at least one sixth doped region comprises: a plurality of sixth doped regions each having a strap configuration in a plain view, wherein the plurality of sixth doped regions are arranged along a first direction. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the first to third wells, the first to fifth doped regions, and the plurality of sixth doped regions are configured in a cell of a layout of the semiconductor device, and the semiconductor device further comprises: a plurality of the cells arranged in an array. ### Claim 13 (depends on 11) The semiconductor device of claim 11, wherein the first to third wells, the first to fifth doped regions, and one sixth doped region in the plurality of sixth doped regions are configured in a first cell of a layout of the semiconductor device, and the first to third wells, the first to fifth doped regions, and the plurality of sixth doped regions are configured in a second cell of the layout of the semiconductor device, and the semiconductor device further comprises: at least one of a plurality of the first cells and at least one of a plurality of the second cells arranged in an array. ### Claim 14 (depends on 8) The semiconductor device of claim 8, further comprising: a third well of the first type, disposed on the substrate and adjacent to the second well; a fifth doped region of the first type, disposed in the third well, wherein the fifth doped region is configured as a first terminal of a third diode and is coupled to the first voltage terminal configured to receive the first supply voltage; a sixth doped region of the second type, disposed in the third well, wherein the sixth doped region is configured as a second terminal of the third diode and is coupled to the first voltage terminal; a fourth well of the second type, disposed on the substrate and adjacent to the third well; a seventh doped region of the first type, disposed in the fourth well, wherein the seventh doped region is configured as a first terminal of the fourth diode and is coupled to the I/O pad; and an eighth doped region of the second type, disposed in the fourth well, wherein the eighth doped region is configured as a second terminal of the fourth diode and is coupled to the second voltage terminal configured to receive the second supply voltage. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the third doped region, the second well, the substrate, the third well, and the sixth doped region are configured as a third ESD path between the first voltage terminal and the second voltage terminal. ### Claim 16 (depends on 14) The semiconductor device of claim 14, wherein the first to fourth wells and the first to eighth doped region are configured in a cell of a layout of the semiconductor device, and the semiconductor device further comprises: a plurality of the cells arranged in an array. ### Claim 17 A method, comprising: conducting a first electrostatic discharge (ESD) path between an input/output (I/O) pad and a first voltage terminal that is configured to receive a first supply voltage, wherein in the first ESD path, a first diode is coupled between the I/O pad and a second voltage terminal that is configured to receive a second supply voltage, and a clamp circuit is coupled between the first voltage terminal and the second voltage terminal; and conducting a second ESD path between the I/O pad and the first voltage terminal, wherein in the second ESD path, the first diode and a second diode having two terminals that are coupled to the first voltage terminal include a first semiconductor structure, and the first semiconductor structure is configured to operate as a first equivalent silicon controlled rectifier (SCR) circuit. ### Claim 18 (depends on 17) The method of claim 17, further comprising: conducting a third ESD path between the first voltage terminal and the second voltage terminal, wherein in the third ESD path, the second diode and a third diode having two terminals that are coupled to the second voltage terminal include a second semiconductor structure, and the second semiconductor structure is configured to operate as a second equivalent SCR circuit. ### Claim 19 (depends on 17) The method of claim 17, wherein a third diode is disposed at a side of the first diode, wherein the third diode comprises a well of a first type, a first doped region of a second type coupled to the I/O pad, and at least one second doped region of the first type coupled to the first voltage terminal. ### Claim 20 (depends on 19) The method of claim 19, wherein the at least one second doped region comprises a plurality of second doped regions each having a strap configuration in a plain view, wherein the plurality of second doped regions are arranged along a first direction.