# US 2021/0082904 A1 · Semiconductor device and layout thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0082904 A1 - Document ID: US20210082904A1 - Status: Published application - Kind: A1 - Application number: 17/107,311 - Filed: 2020-11-30 - Published: 2021-03-18 - Earliest claimed: 2015-12-16 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Cheng-I HUANG; Ting-Wei CHIANG; Shih-Chi FU; Sheng-Fang CHENG; Jung-Chan YANG - Web page: https://patentgrep.com/patent/US20210082904A1 ## CPC - H10D 89/10: Integrated device layouts - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 84/834: {comprising FinFETs} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein. ## Claims ### Claim 1 A semiconductor device, comprising: a first fin formed on a substrate, and comprising a first portion and a second portion that are spaced apart by a first recess, wherein a side of the first portion and a side of the second portion are located at two sides of the first recess, respectively; a first continuous fin formed on the substrate, and extending along the first portion, the first recess and the second portion; and a plurality of continuous gates formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view, wherein a first number of the plurality of continuous gates are disposed across the first recess and each of the first number of the plurality of continuous gates is disposed between the two sides of the first recess in a layout view. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein a second number of the plurality of continuous gates are disposed across the first portion, a third number of the plurality of continuous gates are disposed across the second portion, a fourth number of the plurality of continuous gates are disposed across the first continuous fin, and the fourth number is equal to a sum of the first number, the second number and the third number. ### Claim 3 (depends on 1) The semiconductor device of claim 1, further comprising: a second fin formed on the substrate, and separated from the first fin and the first continuous fin, wherein the second fin comprises separate portions that are spaced apart by a second recess, and the plurality of continuous gates are disposed across the second fin and the second recess. ### Claim 4 (depends on 1) The semiconductor device of claim 1, further comprising: a second fin formed on the substrate, and comprises a third portion and a fourth portion that are spaced apart by a second recess, wherein a side of the third portion and a side of the fourth portion are located at two sides of the second recess, respectively, wherein in a layout view, the two sides of the second recess are substantially aligned with the two sides of the first recess respectively. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein in a layout view, the first fin and the first continuous fin are disposed in a first area of the substrate, and the plurality of continuous gates is disposed across the first area and a second area of the substrate that is separated from the first area, and the first recess faces the second area. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein a distance between the side of the first portion and the side of the second portion, that are located at the two sides of the first recess, is equal to or greater than a distance between two adjacent gates of the plurality of continuous gates. ### Claim 7 A semiconductor device, comprising: a first continuous gate and a second continuous gate disposed over and cover two of edges of a first area of a substrate, wherein the first area comprises a first recess and each of sides of the first recess is located at one of edges of the first area; a plurality of first continuous fins disposed on the first area and extending from the first continuous gate to the second continuous gate; two first fin portions disposed on the first area, wherein the two first fin portions are separated from each other by the first recess; and a plurality of third continuous gates disposed over the first area, wherein a first number of the plurality of third continuous gates are disposed across the first recess and the plurality of first continuous fins, and an entirety of portions of the first number of the plurality of third continuous gates that are disposed across the first recess is within an area surrounded by the sides of the first recess. ### Claim 8 (depends on 7) The semiconductor device of claim 7, further comprising: a plurality of second continuous fins disposed on a second area of the substrate that is separated from the first area, and extending from the first continuous gate to the second continuous gate, wherein the first recess faces the second area, and a side of the second area facing the first recess is substantially flat. ### Claim 9 (depends on 8) The semiconductor device of claim 8, further comprising: two second fin portions disposed on the second area, wherein the two second fin portions are separated from each other by a second recess, wherein one of the two first fin portions and one of the two second fin portions have lengths that are different from each other. ### Claim 10 (depends on 7) The semiconductor device of claim 7, further comprising: second fin portions disposed on a second area of the substrate and spaced apart from each other by a second recess, and arranged to intersect the first continuous gate, the second continuous gate, and the plurality of third continuous gates in a layout view, wherein a second number of the plurality of third continuous gates are disposed across the second recess and the plurality of first continuous fins, and each of the second number of the plurality of third continuous gates is separated from the second fin portions in a layout view. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the two first fin portions are not aligned with the second fin portions, in a layout view. ### Claim 12 (depends on 10) The semiconductor device of claim 10, further comprising: two third fin portions disposed on the second area, wherein the two third fin portions are separated from each other by a third recess, wherein in a layout view, the two third fin portions are substantially aligned with the two first fin portions, and the first recess and the third recess face to each other. ### Claim 13 (depends on 10) The semiconductor device of claim 10, further comprising: a plurality of second continuous fins disposed on the second area and extending from the first continuous gate to the second continuous gate, wherein the plurality of second continuous fins are disposed between the two first fin portions and the second fin portions, in a layout view. ### Claim 14 (depends on 7) The semiconductor device of claim 7, further comprising: a third fin portion disposed on the first area, wherein the third fin portion is separated from a first portion of the two first fin portions by a third recess, wherein at least one of the plurality of third continuous gates is disposed across the third recess and the plurality of first continuous fins, and is distanced from a side of the first portion and a side of the third fin portion, that are located at two separate sides of the third recess, in a layout view. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein a length of the first portion is equal to or greater than a distance between two adjacent gates of the plurality of third continuous gates. ### Claim 16 A method, comprising: placing a plurality of first layout patterns corresponding to a plurality of fins that comprise a plurality of first continuous fins and a plurality of second fins, wherein the plurality of second fins are spaced apart by a first recess and a second recess; and placing a second layout pattern corresponding to a plurality of continuous gates, wherein at least one of the plurality of continuous gates is disposed across the first recess and an entirety of portions of the at least one of the plurality of continuous gates is disposed within the first recess, and at least one of the plurality of continuous gates is disposed across the second recess and an entirety of a portion of the at least one of the plurality of continuous gates is disposed within the second recess. ### Claim 17 (depends on 16) The method of claim 16, wherein a number of the plurality of continuous gates disposed across the first recess is different from a number of the plurality of continuous gates disposed across the second recess, and is greater than one. ### Claim 18 (depends on 16) The method of claim 16, further comprising: placing a plurality of third layout patterns corresponding to a plurality of third continuous fins and a plurality of fourth fins, wherein the plurality of third continuous fins are separated from the plurality of first continuous fins and the plurality of second fins, and the plurality of fourth fins are spaced apart by a third recess. ### Claim 19 (depends on 18) The method of claim 18, wherein at least one of the plurality of continuous gates is disposed across the first recess and the third recess, and at least one of the plurality of continuous gates is disposed across the first recess and is separated from the third recess. ### Claim 20 (depends on 16) The method of claim 16, wherein a first length of each of the plurality of first continuous fins is substantially equal to a sum of a second length of the plurality of second fins, a third length of the first recess and a fourth length of the second recess.