# US 2021/0082811 A1 · Fabrication of integrated circuit including passive electrical component

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- Number: US 2021/0082811 A1
- Document ID: US20210082811A1
- Status: Published application
- Kind: A1
- Application number: 16/954,430
- Filed: 2019-02-12
- Published: 2021-03-18
- Earliest claimed: 2018-02-13
- Assignees: Cirrus Logic International Semiconductor Ltd.
- Applicants: Cirrus Logic International Semiconductor Ltd.
- Inventors: Scott WARRICK; cHRISTIAN LARSEN; Eric J. KING; John L. MELANSON; Anthony S. DOY; David M. BIVEN
- Web page: https://patentgrep.com/patent/US20210082811A1

## CPC

- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating an integrated circuit upon a substrate may include forming a passive electrical component in a non-final layer of the integrated circuit and forming one or more electrical contacts in a final layer of the integrated circuit such that the one or more electrical contacts and the passive electrical component are positioned in a manner such that an imaginary line perpendicular to and from a surface of the substrate intersects the passive electrical component and the one or more electrical contacts.

## Claims

### Claim 1

A method for fabricating an integrated circuit upon a substrate, comprising:
forming a passive electrical component in a non-final layer of the integrated circuit; and
forming one or more electrical contacts in a final layer of the integrated circuit such that the one or more electrical contacts and the passive electrical component are positioned in a manner such that an imaginary line perpendicular to and from a surface of the substrate intersects the passive electrical component and the one or more electrical contacts.

### Claim 2 (depends on 1)

The method of claim 1, wherein the passive electrical component comprises a magnetic-based component.

### Claim 3 (depends on 2)

The method of claim 2, wherein the magnetic-based component comprises an inductor.

### Claim 4 (depends on 2)

The method of claim 2, wherein the magnetic-based component comprises a transformer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the one or more electrical contacts comprises an electrical bump.

### Claim 6 (depends on 1)

The method of claim 1, wherein the substrate is part of a wafer-level chip scale package (WLCSP).

### Claim 7

An integrated circuit fabricated upon a substrate, comprising:
a passive electrical component formed in a non-final layer of the integrated circuit; and
one or more electrical contacts formed in a final layer of the integrated circuit such that the one or more electrical contacts and the passive electrical component are positioned in a manner such that an imaginary line perpendicular to and from a surface of the substrate intersects the passive electrical component and the one or more electrical contacts.

### Claim 7 (depends on 7)

The integrated circuit of claim 7, wherein the one or more electrical contacts comprises an electrical bump.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, wherein the passive electrical component comprises a magnetic-based component.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, wherein the magnetic-based component comprises an inductor.

### Claim 10 (depends on 8)

The integrated circuit of claim 8, wherein the magnetic-based component comprises a transformer.

### Claim 12 (depends on 7)

The integrated circuit of claim 7, wherein the substrate is part of a wafer-level chip scale package (WLCSP).