# US 2021/0082784 A1 · Heat dissipation structures

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- Number: US 2021/0082784 A1
- Document ID: US20210082784A1
- Status: Published application
- Kind: A1
- Application number: 17/107,312
- Filed: 2020-11-30
- Published: 2021-03-18
- Earliest claimed: 2019-07-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yun-Wei CHENG; Chun-Hao CHOU; Kuo-Cheng LEE; Ying-Hao CHEN
- Web page: https://patentgrep.com/patent/US20210082784A1

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 90/00: Package configurations
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.

## Claims

### Claim 1

A structure, comprising:
a plurality of vertically stacked chips bonded together through a respective plurality of passivation layers;
electrically conductive structures coupling the plurality of vertically stacked chips to one another;
thermally conductive structures passing through each of the plurality of vertically stacked chips and configured to transfer heat generated from the plurality of vertically stacked chips to a heat sink; and
heat dissipation layers coupled to the thermally conductive structures, wherein the heat dissipation layers are isolated from the electrically conductive structures.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the heat dissipation layers comprise openings to allow the electrically conductive structures to pass through the heat dissipation layers.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the heat dissipation layers comprise at least one heat dissipation layer with rows and columns of heat dissipations stripes embedded in a passivation layer.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the heat dissipation layers comprise at least one heat dissipation layer embedded in a passivation layer.

### Claim 5 (depends on 1)

The structure of claim 1, wherein at least two of the thermally conductive structures form a multilevel network of thermally conductive structures disposed in multilevel metallization layers of the plurality of vertically stacked chips.

### Claim 6 (depends on 1)

The structure of claim 1, wherein the thermally conductive structures are isolated from the electrically conductive structures.

### Claim 7 (depends on 1)

The structure of claim 1, wherein the thermally conductive structures have substantially similar shapes and sizes as the electrically conductive structures.

### Claim 8

A structure, comprising:
a plurality of vertically stacked chips bonded together through a respective plurality of passivation layers;
a heat dissipation layer embedded in a passivation layer and comprising an array of first heat dissipating stripes disposed over an array of second heat dissipating stripes; and
thermally conductive structures connecting the first and second heat dissipating stripes.

### Claim 9 (depends on 8)

The structure of claim 8, wherein the first heat dissipating stripes are parallel to each other and arranged in a first direction and the second heat dissipating stripes are parallel to each other and arranged in a second direction.

### Claim 10 (depends on 8)

The structure of claim 8, wherein a width of the first and second heat dissipating stripes is between about 30 nm and about 3 μm.

### Claim 11 (depends on 8)

The structure of claim 8, wherein a thickness of the first and second heat dissipating stripes is between about 10 nm and about 1 μm.

### Claim 12 (depends on 8)

The structure of claim 8, wherein the heat dissipation layer is coupled to external thermally conductive structures connecting the heat dissipation layer to a heat sink disposed on the plurality of vertically stacked chips.

### Claim 13 (depends on 8)

The structure of claim 8, wherein the thermally conductive structures comprise cobalt, titanium, tungsten, copper, aluminum, tantalum, titanium nitride, tantalum nitride, gold, silver, another metal, a metal alloy, or combinations thereof.

### Claim 14 (depends on 8)

The structure of claim 8, wherein each of the first and second heat dissipating stripes have a pitch between about 100 nm and about 10 μm.

### Claim 15 (depends on 8)

The structure of claim 8, wherein the heat dissipation layer occupies between about 50% and about 100% of an area occupied by the plurality of vertically stacked chips.

### Claim 16

A stacked structure, comprising:
a substrate;
chips vertically stacked over the substrate, wherein the chips are separated by passivation layers and each chip comprises a metallization layer with conductive structures; and
a heat dissipation layer integrated in the metallization layer, wherein the conductive structures of the metallization layer are electrically isolated from and traverse through the heat dissipation layer.

### Claim 17 (depends on 16)

The stacked structure of claim 16, wherein the heat dissipation layer comprises a network of thermally conductive structures.

### Claim 18 (depends on 16)

The stacked structure of claim 16, wherein the heat dissipation layer is coupled to thermally conductive structure traversing through the chip.

### Claim 19 (depends on 16)

The stacked structure of claim 16, further comprising another heat dissipation layer embedded in a passivation layer and connected to the heat dissipation layer through thermally conductive structure traversing through the chip.

### Claim 20 (depends on 16)

The stacked structure of claim 16, further comprising another heat dissipation layer embedded in a passivation layer and comprising heat dissipating stripes.