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US 2021/0067166 A1Published application
Multiphase injection locked sub-sampling phase locked loop (pll) circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsXiong LIU, Chih-Wei YAO
Life of this patent
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Abstract
A system, method and electronic device are provided. The system includes a shared fractional-N phase-lock loop (PLL), a ring oscillator circuit (OSC), and a multiphase injection pulse generator configured to receive an input signal having a first frequency from the shared fraction-N PLL and generate injection pulses for the OSC based on the input signal.
Claims20
A system, comprising:
- a shared fractional-N phase-lock loop (PLL);
- a ring oscillator circuit (OSC);
- and
- a multiphase injection pulse generator configured to receive an input signal having a first frequency from the shared fraction-N PLL and generate injection pulses for the OSC based on the input signal.
1 more element
A method, comprising:
- generating, by a shared fractional-N phase-lock loop (PLL) an input signal having a first frequency;
- receiving, by a multiphase injection pulse generator, the input signal having the first frequency;
- and
- generating, by the multiphase injection pulse generator, injection pulses for a ring oscillator circuit (OSC) based on the received input signal.
1 more element
A electronic device, comprising:
- at least one receiver;
- a shared fractional-N phase-lock loop (PLL);
- a ring oscillator circuit (OSC);
- a multiphase injection pulse generator;
- and
- a processor configured to receive, from the shared fractional-N PLL, an input signal having a first frequency and generate, by the multiphase injection pulse generator, injection pulses for the OSC based on the input signal.
3 more elements
Dependencies are inferred from the claim text.