Amplifier circuit
AssigneeMurata Manufacturing Co., Ltd.
InventorsDaisuke WATANABE, Nobuyasu BEPPU
Life of this patent
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Abstract
An amplifier circuit (1) includes a FET (10) having a source terminal (S1), a drain terminal (D1), and a gate terminal (G1), a FET (20) having a source terminal (S2), a drain terminal (D2), and a gate terminal (G2) and coupled in parallel with the FET (10), a FET (30) having a source terminal (S3) coupled to the drain terminals (D1 and D2), a drain terminal (D3), and a gate terminal (G3) and cascoded with the FETs (10 and 20), and feedback circuits (21 and 22) configured to feed back to the gate terminal (G2) a high frequency signal outputted from the source terminal (S2) or the drain terminal (D2).
Claims13
An amplifier circuit comprising:
- an input terminal to which a high frequency signal is input;
- an output terminal configured to output an amplified high frequency signal;
- a first transistor having a first source terminal, a first drain terminal, and a first gate terminal, the high frequency signal being input to the first gate terminal via the input terminal;
- a second transistor having a second source terminal, a second drain terminal, and a second gate terminal, the high frequency signal being input to the second gate terminal via the input terminal, and the second transistor being coupled in parallel with the first transistor;
- a third transistor having a third source terminal coupled to the first drain terminal or the second drain terminal, a third drain terminal configured to output the amplified high frequency signal, and a third gate terminal that is grounded, the third transistor being cascode connected with the first transistor or the second transistor;
- and
- a feedback circuit configured to feed back the high frequency signal output from the second source terminal or the second drain terminal to the second gate terminal,
- wherein a ratio of a gate width of the second transistor W2 to a gate length of the second transistor L2 (W2/L2) is less than a ratio of a gate width of the first transistor W1 to a gate length of the first transistor L1 (W1/L1).
Dependencies are inferred from the claim text.