Cap structure coupled to source to reduce saturation current in hemt device

A high electron mobility transistor (HEMT) device, comprising:

• a heterojunction structure arranged over a semiconductor substrate, the heterojunction structure comprising:
• a binary III/V semiconductor layer to act as a channel layer of the HEMT device, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer to act as an active layer;
• source and drain regions arranged over the heterojunction structure and spaced apart from one another in a first direction, wherein the first direction is parallel to an upper surface of the semiconductor substrate;
• a gate structure arranged over the heterojunction structure and arranged between the source and drain regions, wherein the gate structure comprises a gate electrode that comprises a first material;
• and
• a cap structure arranged over the heterojunction structure and directly contacting the source region and the ternary III/V semiconductor layer, wherein the cap structure is arranged between the source region and the gate structure in the first direction, wherein the cap structure is spaced from the gate structure, and wherein the cap structure comprises the first material.

A method of forming high electron mobility transistor (HEMT) device, comprising:

• depositing a passivation layer over a heterojunction structure over a substrate;
• forming a source contact and a drain contact within the passivation layer, wherein the source contact and the drain contact are laterally separated from one another and contact the heterojunction structure;
• performing a first patterning step to remove portions of the passivation layer to define a first cavity and a second cavity in the passivation layer, wherein the first cavity is laterally between the source contact and the drain contact, and wherein the second cavity is laterally between the first cavity and the source contact, and wherein the second cavity is laterally spaced apart from the source contact and the first cavity by the passivation layer;
• depositing a gate electrode material over the passivation layer and in the first cavity and the second cavity;
• and
• performing a second patterning step to form a gate structure within the first cavity and a cap structure within the second cavity from the gate electrode material, wherein the cap structure is spaced apart from the gate structure by the passivation layer, and wherein an upper portion of the cap structure directly contacts a sidewall of the source contact.