METAL OXIDE INTERLAYER STRUCTURE FOR nFET AND pFET

A method of forming a semiconductor device, comprising:

• providing a semiconductor substrate having first and second gate trenches formed thereon;
• depositing an interfacial layer in each of the first and second gate trenches;
• depositing a first metal oxide layer on the interfacial layer in each of the first and second gate trenches;
• removing the first metal oxide layer from the first gate trench exposing the interfacial layer in the first gate trench;
• depositing a ferroelectric layer on the interfacial layer in the first gate trench and on the first metal oxide layer in the second gate trench;
• depositing a second metal oxide layer on the ferroelectric layer in each of the first and second gate trenches;
• removing the second metal oxide layer from the second gate trench exposing the ferroelectric layer in the second gate trench;
• and
• depositing a gate electrode on the second metal oxide layer in the first gate trench and on the ferroelectric layer in the second gate trench.

A semiconductor structure, comprising:

• an nFET structure having a first channel region and a first gate structure, the first gate structure including:
• a first interfacial layer over the first channel region;
• a first metal oxide layer over the first interfacial layer, the first metal oxide layer having a first chemical composition;
• a first ferroelectric layer over the first metal oxide layer, the first ferroelectric layer having a second chemical composition different than the first chemical composition;
• and
• a first gate electrode over the first ferroelectric layer;
• and
• a pFET structure having a second channel region and a second gate structure, the second gate structure including:
• a second interfacial layer over the second channel region;
• a second ferroelectric layer over the second interfacial layer, the second ferroelectric layer having the second chemical composition;
• a second metal oxide layer over the second ferroelectric layer, the second metal oxide layer having the first chemical composition;
• and
• a second gate electrode over the second metal oxide layer.