Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling

An integrated circuit package, comprising:

• a package substrate having a first face and an opposing second face, wherein a bump pitch of the second face of the package substrate is between 200 um and 1000 um, and wherein the package substrate includes a plurality of layers;
• a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers at the first face of the package substrate, and wherein the high-density interconnect layer includes:
• a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 um and 80 um;
• and
• a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via;
• and
• a first die, wherein the first die is electrically coupled to an individual pillar of the plurality of pillars on the high-density interconnect layer.

A computing device, comprising:

• a circuit board;
• and
• an integrated circuit package coupled to the circuit board, wherein the integrated circuit package comprises:
• a package substrate having a first face and an opposing second face, wherein a bump pitch of the second face of the package substrate is between 200 um and 1000 um, and wherein the package substrate includes a plurality of layers;
• a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers of the package substrate and is at the first face of the package substrate, and wherein the high-density interconnect layer includes:
• a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 um and 80 um;
• and
• a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via;
• and
• a first die, wherein the first die is electrically coupled to the package substrate via one or more of the plurality of pillars on the high-density interconnect layer.

An integrated circuit assembly, comprising:

• a package substrate having a first face and an opposing second face, wherein a bump pitch of the second face of the package substrate is between 200 um and 1000 um, and wherein the package substrate includes a plurality of layers;
• and
• a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers of the package substrate at the first face of the package substrate, and wherein the high-density interconnect layer includes:
• a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 um and 80 um;
• and
• a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via.