Methods of fabricating semiconductor devices with mixed threshold voltages boundary isolation of multiple gates and structures formed thereby

A semiconductor device, comprising:

• a plurality of first semiconductor nanosheets spaced apart from each other and in a p-type device region;
• a plurality of second semiconductor nanosheets spaced apart from each other and in an n-type device region;
• an isolation structure formed at a boundary between the p-type and n-type device regions;
• a first hard mask layer formed over the first semiconductor nanosheets;
• a second hard mask layer formed over the second semiconductor nanosheets;
• and
• a p-type work function layer surrounding each of the first semiconductor nanosheets and the first hard mask layer.

A semiconductor device, comprising:

• a plurality of first semiconductor nanosheets spaced apart from each other and in a p-type device region;
• a plurality of second semiconductor nanosheets spaced apart from each other and in an n-type device region;
• an isolation structure formed at a boundary between the p-type and n-type device regions, wherein the isolation structure extends above a bottommost nanosheet of the first semiconductor nanosheets;
• a p-type work function layer surrounding each of the first semiconductor nanosheets;
• and
• a n-type work function layer surrounding each of the first semiconductor nanosheets and each of the second semiconductor nanosheets, wherein a topmost surface of the p-type work function layer is higher than a top surface of the isolation structure.