Memory device

A memory device comprising

• a lower chip and an upper chip,
• wherein the upper chip comprises a common source line, a memory cell array on the common source line, a read common source line transistor on the common source line, a ground pad connected to the read common source line transistor, and a plurality of upper bonding pads connected to the memory cell array,
• the lower chip comprises a substrate, a lower circuit on the substrate, and a plurality of lower bonding pads connected to the lower circuit, and
• the upper chip is in contact with the lower chip such that the plurality of upper bonding pads of the upper chip are in contact with the plurality of lower bonding pads of the lower chip.

A memory device comprising:

• a common source line in an upper portion of an upper chip;
• a memory cell array comprising a plurality of gate layers and a plurality of channel structures, the plurality of gate layers stacked on a lower surface of the common source line and spaced apart from each other, the plurality of channel structures passing through the plurality of gate layers and in contact with the common source line;
• a read common source line transistor comprising a gate layer and a channel structure, the gate layer on the lower surface of the common source line, the channel structure passing through the gate layer and in contact with the common source line;
• a ground pad connected to the channel structure of the read common source line transistor and in the upper portion of the upper chip;
• a plurality of upper bonding pads connected to the memory cell array and in a lower portion of the upper chip;
• a substrate in a lower portion of a lower chip;
• a lower circuit on an upper surface of the substrate;
• and
• a plurality of lower bonding pads connected to the lower circuit and in an upper portion of the lower chip, the plurality of lower bonding pads being in contact with the plurality of upper bonding pads of the upper chip.