Non-volatile memory device

A non-volatile memory device comprising:

• a memory cell region comprising a first metal pad and a memory cell array that includes a vertical channel structure;
• and
• a peripheral circuit region comprising a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad,
• wherein the memory cell region comprises:
• a plurality of word lines stacked in a vertical direction;
• a ground selection line in a layer on the plurality of word lines;
• a plurality of vertical pass transistors in a stair area of the plurality of word lines, the plurality of vertical pass transistors each comprising a vertical channel extending in the vertical direction;
• and
• a plurality of driving signal lines in a layer on the plurality of vertical pass transistors, and
• wherein each of the plurality of vertical pass transistors is connected between a corresponding word line among the plurality of word lines and a corresponding driving signal line among the plurality of driving signal lines.

A non-volatile memory device comprising:

• a memory cell region comprising a first metal pad and a memory cell array that includes a plurality of memory cells;
• and
• a peripheral circuit region comprising a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad,
• wherein the peripheral circuit region comprises a transistor,
• wherein the memory cell region comprises:
• a plurality of word lines stacked in a vertical direction;
• a ground selection line on the plurality of word lines;
• a common source line on the ground selection line;
• a plurality of vertical pass transistors in a stair area of the plurality of word lines, wherein the plurality of vertical pass transistors are respectively connected to the plurality of word lines;
• a plurality of first contacts extending in the vertical direction, connecting ones of the plurality of vertical pass transistors to ones of the plurality of word lines, and having substantially equal lengths in the vertical direction;
• and
• a plurality of driving signal lines in a same layer as the common source line,
• wherein each of the plurality of vertical pass transistors is connected between a corresponding driving signal line among the plurality of driving signal lines and a corresponding word line among the plurality of word lines and comprises a gate that is configured to receive a block selection signal, and
• wherein the gate is in a same layer as the ground selection line and is connected to the transistor in the peripheral circuit region through a second contact and a first bonding pad that are formed in the memory cell region and through a second bonding pad and a third contact that are formed in the peripheral circuit region.