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US 2021/0065792 A1Published application
Memory device and method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJau-Yi WU, Win-San KHWA, Jin CAI, Yu-Sheng CHEN
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Abstract
A method includes: applying a first signal to memory cells in a memory device, to adjust resistance values of the memory cells; after applying the first signal, applying a second signal to the memory cells other than a first memory cell in the memory cells, to further adjust the resistance values of the memory cells other than the first memory cell. A memory device is also disclosed herein.
Claims20
A method, comprising:
- applying a first signal to a plurality of memory cells in a memory device, to adjust resistance values of the plurality of memory cells;
- and
- after applying the first signal, applying a second signal to the plurality of memory cells other than a first memory cell in the plurality of memory cells, to further adjust the resistance values of the plurality of memory cells other than the first memory cell.
A method, comprising:
- writing first memory cells of a plurality of memory cells with a first group of pulses, wherein the first group of pulses are configured to decrease resistance values of the first memory cells;
- and
- writing second memory cells of the plurality of memory cells with a second group of pulses, wherein the second group of pulses are configured to increase resistance values of the second memory cells.
A memory device, comprising:
- a plurality of memory cells;
- and
- a write circuit coupled to the plurality of memory cells, wherein the write circuit is configured to write the plurality of memory cells, to adjust resistance values of the plurality of memory cells, and further configured to write at least one first memory cell in the plurality of memory cells to further adjust the resistance value of the at least one first memory cell.
Dependencies are inferred from the claim text.