Memory device latch circuitry

A method comprising:

• receiving data to be stored in a plurality of latch cells at an input;
• generating a data signal in a first portion of a write driver;
• generating a data false signal using a second portion of the write driver, wherein generating the data signal and the data false signal are generated in parallel between the input and the plurality of latch cells;
• driving a first side of the plurality of latch cells using the data false signal;
• and
• driving a second side of the plurality of latch cells using the data signal.

Latch circuitry apparatus comprising:

• a plurality of latch cells each configured to store a bit of data;
• a data line coupled to a first side of the plurality of latch cells;
• a data false line coupled to a second side of the plurality of latch cells;
• a write driver, comprising:
• an input configured to receive the data;
• a first portion of circuitry coupled to the input and configured to generate and output a data signal on the data line;
• and
• a second portion of circuitry coupled to the input and configured to generate and output a data false signal on the data false line, wherein generating the data signal and the data false signal are performed in parallel with no overlap between the first portion of the circuitry and the second portion of the circuitry between the input and the plurality of latch cells.