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US 2021/0065784 A1Published application
Multi-port high performance memory
AssigneeMarvell International Ltd.
InventorsGeorge M. BRACERAS, Xiaoli HU, Wei ZHAO, Igor ARSOVSKI, Yuzheng JIN, Hao PU, Shuangdi ZHAO, Qing LI
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Abstract
A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.
Claims25
A memory circuit comprising:
- a memory bitcell comprising a single ended read port and configured to store a bit of data;
- a timer circuit configured to receive a clock signal and generate two successive pulses during a single cycle of the clock signal and, based on the two successive pulses, generate first control signals to enable asynchronous reading of the single ended read port during the single cycle of the clock signal;
- and
- a read circuit connected to the single ended read port of the memory bitcell the read circuit being configured to, based on the first control signals, perform two successive reads of the single ended read port during the single cycle of the clock signal and output respective states of the memory bitcell read during the two successive reads of the single ended read port.
1 more element
A memory circuit comprising:
- a memory bitcell comprising a single ended read port and a differential write port and configured to store a bit of data;
- a first timer circuit configured to receive a clock signal and generate two successive read pulses during a single cycle of the clock signal to enable two successive reads of the single ended read port during the single cycle of the clock signal;
- a second timer circuit configured to generate two timing pulses during the single cycle of the clock signal to enable a read operation of the memory bitcell followed by a write operation of the memory bitcell during the single cycle of the clock signal;
- and
- a read circuit, connected to the single ended read port, and configured to perform the two successive reads of the read port during the single cycle of the clock signal and output respective states of the memory bitcell read during the two successive reads of the single ended read port.
2 more elements
A method, comprising:
- receiving a clock signal;
- generating two successive read pulses during a single cycle of the clock signal to enable two successive reads of a single ended read port of a memory bitcell during, the single cycle of the clock signal;
- generating two timing pulses during, the single cycle of the clock signal to enable a read of a differential write port of the memory bitcell followed by a write operation of the differential write port during the single cycle of the clock signal;
- latching states of the memory bitcell, read during the two success reads, respectively for a first output port and a second output port;
- latching a state of the memory bitcell read during the read of the differential write port for a third output port;
- and
- generating synchronized timing signals to enable a same access time for the first output port, the second output port and the third output port.
4 more elements
Dependencies are inferred from the claim text.