Memory controller and operating method thereof

Abstract

A memory controller capable of sequentially increasing or decreasing a total current consumed by a plurality of memory devices, controls a plurality of memory devices coupled through a plurality of channels. The memory controller includes a request checker for identifying memory devices corresponding to requests received from a host among the plurality of memory devices, and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager for outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator for sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse.

Dependencies are inferred from the claim text.