Semiconductor storage device

A method of transferring data from a plurality of sense amplifier units of a semiconductor storage device to a cache memory of the semiconductor storage device, wherein the plurality of sense amplifier units, including first and second sense amplifier units, are arranged along a first direction at increasing distances away from the cache memory, comprising:

• transferring first data from a first bit line onto a first sense node of the first sense amplifier unit and second data from a second bit line onto a second sense node of the second sense amplifier unit;
• latching the first data in a first latch of the first sense amplifier unit and the second data in a second latch of the second sense amplifier unit;
• transferring the first data from the first sense amplifier unit to the cache memory;
• and
• transferring the second data from the second sense amplifier unit onto the first sense node of the first sense amplifier unit.

A method of transferring data from a plurality of sense amplifier units of a semiconductor storage device to a cache memory of the semiconductor storage device, wherein the plurality of sense amplifier units include first and second sense amplifier units that are in a first group of the sense amplifier units that are arranged along a first direction at increasing distances away from the cache memory and third and fourth sense amplifier units that are in a second group of the sense amplifier units that are arranged along the first direction at increasing distances away from the cache memory, comprising:

• transferring first data from a first bit line onto a first sense node of the first sense amplifier unit, second data from a second bit line onto a second sense node of the second sense amplifier unit, third data from a third bit line onto a third sense node of the third sense amplifier unit, and fourth data from a fourth bit line onto a fourth sense node of the fourth sense amplifier unit;
• latching the first, second, third, and fourth data in a first latch of the first sense amplifier unit, a second latch of the second sense amplifier unit, a third latch of the third sense amplifier unit, and a fourth latch of the fourth sense amplifier unit, respectively;
• and
• transferring the first data from the first sense amplifier unit to the cache memory and the third sense node of the third sense amplifier unit, while transferring the second data from the second sense amplifier unit to the first sense node of the first sense amplifier unit and the third data from the third sense amplifier unit to the fourth sense node of the fourth sense amplifier unit.