Row drive circuit of array substrate and display device

A row drive circuit of an array substrate, wherein the row drive circuit comprises:

• N row drive units arranged in cascade, each of the row drive units comprises a signal input end, a pull-up control signal end, and a gate driving signal output end;
• and
• a plurality of auxiliary circuit units with each of the auxiliary circuit units corresponding to one of the row drive units, each of the auxiliary circuit units comprises a first timing signal input end, a second timing signal input end, a first controlled end, and an output end;
• the first timing signal input end of the Nth auxiliary circuit unit receives the (N−1)th timing control signal, the second timing signal input end of the Nth auxiliary circuit unit receives the (N+1)th timing control signal, the first controlled end and the output end of the Nth auxiliary circuit unit are connected to the gate driving signal output end of the Nth row drive unit;
• the Nth row drive unit is configured to output a Nth gate driving signal for pre-charging and charging the Nth row of sub-pixels, when a signal input end of the Nth row drive unit receives the gate driving signal output by the (N−2)th row drive unit;
• the Nth auxiliary circuit unit is configured to control the Nth row drive unit skip pre-charging the sub-pixels, when the (N−1)th timing control signal received by the first timing signal input end of the Nth auxiliary circuit unit and the (N+1)th timing control signal received by the second timing signal input end of the Nth auxiliary circuit unit are both high level;
• and
• N is a positive integer greater than or equal to two;
• and
• each of the auxiliary circuit units comprises a first active switch, a second active switch, and a third active switch, at least one of the first active switch, the second active switch, and the third active switch being a thin film transistor.

A display device, wherein the display device comprises:

• a display panel comprising two sides facing each other, and a pixel array;
• and
• a row drive circuit of an array substrate comprising N row drive units arranged in cascade, and a plurality of auxiliary circuit units with each of the auxiliary circuit units corresponding to one of the row drive units, each side of the display panel is provided with the N row drive units arranged in cascade, and the auxiliary circuit units;
• the row drive circuit comprises:
• N row drive units arranged in cascade, each of the row drive units comprises a signal input end, and a gate driving signal output end;
• and
• a plurality of auxiliary circuit units with each of the auxiliary circuit units corresponding to one of the row drive units, each of the auxiliary circuit units comprises a first timing signal input end, a second timing signal input end, a first controlled end, and an output end;
• the first timing signal input end of the Nth auxiliary circuit unit receives the (N−1)th timing control signal, the second timing signal input end of the Nth auxiliary circuit unit receives the (N+1)th timing control signal, the first controlled end and the output end of the Nth auxiliary circuit unit are connected to the gate driving signal output end of the Nth row drive unit;
• the Nth row drive unit is configured to output a Nth gate driving signal for pre-charging and charging the Nth row of sub-pixels, when a signal input end of the Nth row drive unit receives the gate driving signal output by the (N−2)th row drive unit;
• the Nth auxiliary circuit unit is configured to control the Nth row drive unit skip pre-charging the sub-pixels, when the (N−1)th timing control signal received by the first timing signal input end of the Nth auxiliary circuit unit and the (N+1)th timing control signal received by the second timing signal input end of the Nth auxiliary circuit unit are both high level;
• and
• N is a positive integer greater than or equal to two.