Memory Access During Memory Calibration
AssigneeRambus Inc.
InventorsIan Shaeffer, Frederick A. Ware
Life of this patent
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Abstract
A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.
Claims21
(canceled)
A memory controller, comprising:
- a first data interface circuit to couple to a first memory device via a first data bus, the first memory device including a plurality of first sub-banks of memory;
- and
- a second data interface circuit to couple to the first memory device via a second data bus;
- wherein the memory controller is configured to transmit to the first memory device a first calibration command and a first refresh command to refresh a first sub-bank of the plurality of first sub-banks, and while the first sub-bank is being refreshed responsive to the first refresh command and a first calibration operation is performed on the first data interface circuit responsive to the first calibration command, data is transferred, via the second data interface, between the memory controller and a second sub-bank from the plurality of first sub-banks that is not being refreshed.
A method of operation in a memory controller including a first data interface circuit to couple to a first memory device via a first data bus where the first memory device includes a plurality of first sub-banks of memory, and a second data interface circuit to couple to the first memory device via a second data bus, the method comprising:
- transmitting, to the first memory device, a first refresh command to refresh a first sub-bank of the plurality of first sub-banks included in the first memory device;
- transmitting, to the first memory device, a first calibration command to calibrate the first data bus;
- performing a first calibration operation on the first data interface in response to the first calibration command while the first sub-bank is being refreshed in response to the first refresh command;
- and
- transferring, with the second data interface, data between the memory controller and a second sub-bank from the plurality of first sub-banks in response to the memory controller transmitting a first data transfer command to the first memory device.
A memory controller, comprising:
- a first data interface means for coupling to a first memory device via a first data bus, the first memory device including a plurality of first sub-banks of memory;
- and
- a second data interface means for coupling to the first memory device via a second data bus;
- wherein the memory controller is configured to transmit to the first memory device a first calibration command and a first refresh command to refresh a first sub-bank of the plurality of first sub-banks, and while the first sub-bank is being refreshed responsive to the first refresh command and a first calibration operation is performed on the first data interface circuit responsive to the first calibration command, data is transferred, via the second data interface, between the memory controller and a second sub-bank from the plurality of first sub-banks that is not being refreshed.
Dependencies are inferred from the claim text.